Microelectronic package and method of manufacturing same

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S686000, C257S691000, C257S692000, C257S698000, C257S773000, C257S778000, C257SE23010, C257SE23062, C257SE23067, C257SE23079, C438S107000, C438S108000, C438S125000

Reexamination Certificate

active

08035218

ABSTRACT:
A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

REFERENCES:
patent: 5281151 (1994-01-01), Arima et al.
patent: 6323735 (2001-11-01), Welland et al.
patent: 6724638 (2004-04-01), Inagaki et al.
patent: 7141883 (2006-11-01), Wei et al.
patent: 7649252 (2010-01-01), Sakai et al.
patent: 2003/0218235 (2003-11-01), Searls et al.
patent: 2004/0066617 (2004-04-01), Hirabayashi et al.
patent: 2004/0238942 (2004-12-01), Chakravorty et al.
patent: 2005/0045986 (2005-03-01), Koo et al.
patent: 2006/0103011 (2006-05-01), Andry et al.
patent: 2006/0180924 (2006-08-01), Andry et al.
patent: 2007/0194427 (2007-08-01), Choi et al.
patent: 2008/0237828 (2008-10-01), Yang
patent: 2008/0265406 (2008-10-01), Andry et al.
patent: 2009/0001550 (2009-01-01), Li et al.
patent: 2011/056306 (2011-05-01), None
Skeete et al. “Integrated Circuit Packages Including High Density Bump-Less Build Up Layers and a Lesser Density Core or Coreless Substrate” U.S. Appl. No. 11/860,922, filed Sep. 25, 2007, 19 pages.
International Search Report and Written Opinion received for PCT Application No. PCT/US2010/049457, Mailed on Jun. 7, 2011, 12 pages.
International Search Report and Written Opinion received for PCT Application No. PCT/US2010/049521, Mailed on Apr. 28, 2011, 9 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Microelectronic package and method of manufacturing same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microelectronic package and method of manufacturing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microelectronic package and method of manufacturing same will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4293056

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.