Microelectronic interlayer dielectric structure

Details Microelectronic interlayer dielectric structure Microelectronic interlayer dielectric structure

1993-07-16

1994-12-27

Ryan, Patrick J.

Stock material or miscellaneous articles

Structurally defined web or sheet

Discontinuous or differential coating, impregnation or bond

428209, 428433, 428446, B32B 900

Patent

active

053764358

ABSTRACT:
An interlayer dielectric structure for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric-layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.

REFERENCES:
patent: 3632433 (1972-01-01), Tokuyama et al.
patent: 3825442 (1974-07-01), Moore
patent: 4775550 (1988-10-01), Chu et al.

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