Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Patent
1994-11-02
1996-11-26
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
257206, 257208, 257210, 257211, H01L 2710, H01L 27118
Patent
active
055788408
ABSTRACT:
Electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit extend in three directions that are angularly displaced from each other by 60.degree.. The conductors pass through points defined by centers of closely packed hexagons superimposed on the circuit such that the conductors extend perpendicular to edges of the hexagons. The conductors that extend in the three directions can be formed in three different layers, or alternatively the conductors that extend in two or three of the directions can be formed in a single layer as long as they do not cross. The conductors can be formed in layers that are electrically insulated from the cells and extend over the cells, or can extend through hexagons between cells. Cells are defined by clusters of two or more hexagons, enabling a variety of cell shapes to be accommodated. Cells have serrated edges defined by edges of hexagons such that adjacent cells fit together exactly, providing a closely packed arrangement of cells on the substrate with 100% utilization of space and 100% equidistant connectivity. Sets of cells having the same functionality and different shapes are provided.
REFERENCES:
patent: 4517659 (1985-05-01), Chamberlain
patent: 4673966 (1987-06-01), Shimoyama
patent: 5095343 (1992-03-01), Klodzinski et al.
patent: 5117277 (1992-05-01), Yuyama et al.
patent: 5130767 (1992-07-01), Lidow et al.
patent: 5323036 (1994-06-01), Neilson et al.
1980 IEEE International Symposium on Circuits and Systems Proceedings, 80CH1564-4, vol. 3 of 3; P. Pal Chaudhuri, "Routing Multilayer Boards on Steiner Metric"; pp. 961-964.
Sarrafzadeh, Majid and Wong, C. K.; "Hierarchical Steiner Tree Construction in Uniform Orientations"; IEEE, 1992.
Aleshin Stanislav V.
Andreev Alexander E.
Koford James S.
Kudryavstev Valeriy B.
Podkolzin Alexander S.
Jackson Jerome
LIS Logic Corporation
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