Microelectronic fabrication method minimizing threshold voltage

Metal treatment – Compositions – Heat treating

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148187, 357 23, 357 91, H01L 21265, H01L 2978

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042182670

ABSTRACT:
A microelectronic fabrication process for minimizing the threshold voltage variation across the surface of a wafer of semiconductor material. The process precisely specifies the degenerate (or heavily doped) impurity profile distribution by using ion implantation so as to minimize the autodoping of adjacent gate regions immediately after the ion implantation step during gate oxidation, while maximizing the surface concentration of the dopant at the ultimate silicon surface to achieve appropriate surface sheet resistance and junction depth after all circuit fabrication steps have been completed.

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patent: 4128439 (1978-12-01), Jambotkar
Runge, "Threshold Voltage--Impln. of Donors", Appl. Phys. 8 (1975) 43.
Runge, "Threshold Voltage Shift--by Ion Implantation", Electronic Engineering, Jan. 1976, 41.
Fischer et al., "--Si--MOSFETS--Implanted Channel", Solid St. Electronics, 22 (1979) 225.
Abbas et al., "Short Channel--Transistor", IBM--TDB, 17 (1975) 3263.

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