Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-05-13
2004-09-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000
Reexamination Certificate
active
06787375
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electrical test apparatus electrical test methods for electrically testing microelectronic fabrication die. More particularly, the present invention relates to electrical test apparatus electrical test methods for efficiently electrically testing microelectronic fabrication die.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Integral to the fabrication of microelectronic fabrications, and in particular to the fabrication of semiconductor integrated circuit microelectronic fabrications, is the electrical testing of microelectronic fabrication die. The electrical testing of microelectronic fabrication die may occur: (1) during various stages incident to the ongoing fabrication of microelectronic fabrication substrates, as is generally understood to encompass in-line electrical testing of microelectronic fabrication die; as well as (2) subsequent to completion of fabrication of microelectronic fabrication substrates, as is generally understood to encompass final electrical testing of microelectronic fabrication die. Within either in-line electrical testing of microelectronic fabrication die or final electrical testing of microelectronic fabrication die there is typically and preferably employed an electrical test apparatus electrical test method which provides for electrical testing of various microelectronic devices and/or various microelectronic circuits within a plurality of microelectronic fabrication die fabricated within a microelectronic fabrication substrate.
While in-line electrical testing of microelectronic fabrication die and final electrical testing of microelectronic fabrication die while employing electrical test apparatus electrical test methods are both of considerable interest and of considerable importance to the goal of fabricating fully functional and fully reliable microelectronic fabrication die, both in-line electrical testing of microelectronic fabrication die and final electrical testing of microelectronic fabrication die while employing electrical test apparatus electrical test methods are nonetheless not entirely without problems with respect to the goal of fabricating fully functional and fully reliable microelectronic fabrication die. In that regard, both in-line electrical testing of microelectronic fabrication die and final electrical testing of microelectronic fabrication die while employing electrical test apparatus electrical test methods are often not entirely efficient when fabricating microelectronic fabrication die and often require a considerable expenditure of microelectronic fabrication processing resources, including but not limited to microelectronic fabrication cycle time processing resources, microelectronic fabrication tooling processing resources and microelectronic fabrication direct labor processing resources, when fabricating microelectronic fabrication die. Such electrical test testing inefficiency and considerable expenditure of microelectronic fabrication processing resources in turn increases in general microelectronic fabrication production costs when fabricating microelectronic fabrication die.
It is thus desirable in the art of microelectronic fabrication to provide electrical test methods for more efficiently electrically testing microelectronic fabrication die fabricated within microelectronic fabrication substrates.
It is towards the foregoing object that the present invention is directed.
Various methods, systems and apparatus for electrically testing microelectronic fabrications, such as to realize desirable results incident to electrically testing microelectronic fabrications, have been disclosed in the art of microelectronic fabrication.
Included among the methods, systems and apparatus, but not limited among the methods, systems and apparatus, are methods, systems and apparatus disclosed within: (1) Shibata, in U.S. Pat. No. 5,585,737 (an electrical probe apparatus electrical test method for electrically testing semiconductor integrated circuit microelectronic fabrication die within a semiconductor substrate while minimizing a number of times the semiconductor substrate must be indexed, by optimizing within the electrical probe apparatus electrical test method an index region of an electrical probe card with respect to the semiconductor substrate); (2) Stubblefield et al., in U.S. Pat. No. 6,043,101 (an electrical probe apparatus electrical test method which efficiently reduces a quantity of false electrical failures when electrically testing a series of semiconductor integrated circuit microelectronic fabrication die within a semiconductor substrate, by providing for an immediate retesting of an apparent electrically failed semiconductor integrated circuit microelectronic fabrication die prior to repositioning an electrical test apparatus electrical probe head employed for electrically testing the series of semiconductor integrated circuit microelectronic fabrication die); and (3) Atchison et al., in U.S. Pat. No. 6,324,481 (an electrical test apparatus electrical test method for determining yield limits when fabricating semiconductor integrated circuit microelectronic fabrication die, by: (1) generating a semiconductor substrate wafer map with respect to electrically tested semiconductor integrated circuit microelectronic fabrication die; (2) eliminating from the wafer map semiconductor integrated circuit microelectronic fabrication die which have multiple defects; and (3) predicting for semiconductor integrated circuit microelectronic fabrication die which have only single defects a probability that the single defects may be yield limiting with respect to the semiconductor integrated circuit microelectronic fabrication die).
Desirable in the art of microelectronic fabrication are additional electrical test methods which may be employed for more efficiently electrically testing microelectronic fabrication die fabricated within microelectronic fabrication substrates.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide an electrical test method for electrically testing a series of microelectronic fabrication die fabricated within a microelectronic fabrication substrate.
A second object of the present invention is to provide an electrical test method in accord with the first object of the present invention, wherein the series microelectronic fabrication die is efficiently electrically tested.
A third object of the present invention is to provide an electrical test method in accord with the first object of the present invention and the second object of the present invention, wherein the electrical test method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention an electrical test method for electrically testing a series of microelectronic fabrication die fabricated within a microelectronic fabrication substrate.
To practice the method of the present invention, there is first provided a microelectronic fabrication substrate having fabricated therein a series of microelectronic fabrication die. There is then electrically tested the series of microelectronic fabrication die while employing an electrical test apparatus, to thus define within the series of microelectronic fabrication die at least one sub-series of electrically unacceptable microelectronic fabrication die. There is also determined whether the microelectronic fabrication substrate may be reworked. Finally, there is also electrically retested within the microelectronic fabrication substrate only the at least one sub-series of electrically unacceptable microelectronic fabrication die, and only if the microelectronic fabrication substrate may be reworked.
There present invention provides an electrical test
Cheng Yung-Min
Hsu Juei-Feng
Liu Yao-Tung
Yang Chun-Tsung
Luk Olivia T.
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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