Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-04-12
2002-08-27
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S758000
Reexamination Certificate
active
06441494
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the manufacture of semiconductor devices and more specifically to a method for forming a more reliable interlayer contact.
BACKGROUND OF THE INVENTION
It is common in semiconductor devices to make a vertical contact between two horizontal conductive layers by etching a hole (sometime called a “via”) in the dielectric that separates the two layers. Such a contact can be established in a number of ways. The traditional way of forming a contact has been to etch a via in the dielectric that covers a first conductive layer, and then depositing a second conductive layer on the dielectric layer such that the material that comprises the second conductive layer enters the via and makes mechanical/electrical contact with the first conductive layer. Alternatively, the trend in more modem devices has been to etch the via, and then to fill the via with a conductive substance to form a “plug.” A plug is formed by depositing the conductive substance in the via so as to come in mechanical/electrical contact with the first conductive layer, and then polishing the remainder of the conductive substance which resides on top of the dielectric surface away, for example, by chemical-mechanical-polishing (CMP). Once the plug is formed, the second conductive layer can be deposited on top of the plug so as to come in mechanical/electrical contact with the plug, and thus in mechanical/electrical contact with the first conductive layer.
The various ways of making contacts have certain drawbacks. For example, in DRAM (dynamic random access memory) technologies it is desirable to make periodic contacts to the cell plate of the capacitor in each cell for the purpose of applying a reference voltage thereto. (An example of a DRAM cell with a cell plate can be found in the assignee's copending application Ser. No. 09/385,586, which is herein incorporated by reference in its entirety). To economize the process, this processing step can also be used to form contacts to other structures, for example, to the control gates in the peripheral portion of the memory device. However, the mechanical/electrical quality of the contacts formed can vary due to the fact that the dielectric overlying the control gate and the cell plate are of different thicknesses, and due to the fact the control gate and the cell plate are made from different materials which will be more or less susceptible to the via etch. These problems are worsened if the conductive materials to be brought into contact do not adhere well to one another (e.g., tungsten and polysilicon). Moreover, the CMP polishing can cause the material in the via that forms the plug to become loose, thereby rendering the contact mechanically/electrically unstable. The cell plate vias are particularly susceptible to this sort of instability because they are thin in comparison to the control. gate vias. (Other problems associated with making a reliable cell plate contact, and a method for fixing such problems, can be found in the assignee's copending application Ser. No. 09/385,586
Special problems with contact stability are exacerbated when it is desired to electrically connect not two but three or more horizontal conductive layers. The traditional approach has been to create vias to connect each conductive layer to only the conductive layer directly above it. However, this technique is labor intensive and is susceptible to problems when the vias are stacked on top of one another due to the potentially uneven surface of the conductor underlying a given via. Misalignment of the vias with respect to one another can exacerbate the unreliability of the contact.
The present inventions provide a contact structure that fixes these problems, and a method of producing such structures, thereby providing a relatively simple and reliable way for creating quality contacts between conductive layers.
SUMMARY OF THE INVENTION
In view of the foregoing considerations, the present invention is directed in one respect to a method for constructing a contact between a first conductive layer and a second conductive layer in a microelectronic device, which comprises forming a first material on a substrate; forming a first conductive layer with a top surface on the first material; forming a pattern in the first conductive layer, the pattern defining edges in the first conductive layer; forming a dielectric layer on the surface of the first conductive layer; removing a portion of the dielectric layer over the pattern to expose at least a portion of the pattern, a portion of the top surface of the first conductive layer, and a portion of the edges in the first conductive layer; removing a portion of the first material beneath the exposed portion of the pattern; forming an undercut in the first material which is underneath the exposed surface of the first conductive layer; forming a conductive material on the structure wherein the conductive material fills a portion of the undercut, contacts the exposed edges in the first conductive layer, and contacts the exposed top surface of the first conductive layer; and forming a second conductive layer in contact with the conductive material, whereby the first conductive layer and the second conductive layer are brought into contact through the conductive material.
Another aspect of the invention is directed to a contact structure for connecting a first conductive layer and a second conductive layer in a microelectronic device, which comprises a first dielectric layer formed on a substrate; a first conductive layer formed on the first dielectric layer, the first conductive layer having a top surface, the first conductive layer also having a pattern etched therein, the pattern defining an edge in the first conductive layer; a second dielectric layer deposited on the top surface of the first conductive layer; a via formed in the second dielectric layer, the via passing through at least a portion of the pattern and into the first dielectric layer, wherein the via exposes a portion of the top surface of the first conductive layer and a portion of the edge in the first conductive layer; an undercut region in the first dielectric layer below the first conductive layer proximate to at least a portion of the edge in the first conductive layer, the undercut region being in communication with the via; a conductive material, wherein the conductive material substantially fills the undercut region and the via, and wherein the conductive material is in contact with at least a portion of the exposed top surface of the first conductive layer and at least a portion of the exposed edge in the first conductive layer; and a second conductive layer in contact with the conductive material, whereby the first and second conductive layers are brought into contact through the conductive material.
Another aspect of the invention is directed to a method for establishing contact between a first conductive layer, a second conductive layer, and a third conductive layer in a microelectronic device, which comprises forming a first conductive layer with a top surface on a substrate; forming a first dielectric layer on the top surface of the first conductive layer; forming a second conductive layer with a top surface on the first dielectric layer; forming a pattern in the second conductive layer, the pattern defining an edge in the second conductive layer; forming a second dielectric layer on the top surface of the second conductive layer; removing a portion of the second dielectric layer over the pattern to expose at least a portion of the pattern, a portion of the top surface of the second conductive layer, and a portion of the edge in the second conductive layer; removing a portion of the first dielectric layer beneath the exposed portion of the pattern to expose a portion of the top surface of the first conductive layer; forming a conductive material on the structure wherein the conductive material contacts the exposed top surface of the first conductive layer, contacts the exposed edges in the second conductive layer, an
Huang Yin
Ping Er-Xuan
Howrey Simon Arnold & White , LLP
Micro)n Technology, Inc.
Wilson Allan R.
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