Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Patent
1996-10-17
1998-10-27
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
257 14, 257327, 257329, 438197, 438212, H01L 2906
Patent
active
058280766
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon MOS technology component wherein a gate region has a surface structure having edges and/or vertices at which inversion regions, suitable as quantum wires or quantum dots, are preferentially formed when a gate voltage is applied. The surface structure is preferably formed as a silicon pyramid.
2. Description of the Related Art
Single-electron components, which are regarded as promising alternatives for conventional CMOS technology with a view to higher integration density and/or higher operation speeds, have one or more nodes which can only be charging or discharging through high-impedance potential barriers. This charging/discharging is explained by a quantum-mechanical tunneling effect. The charging and discharging of a node by one elementary charge corresponds to a charge transfer of one electron across the potential barrier. This requires an activation energy which depends on the capacitance of the node. So long as the thermal energy of the system is very much less than this activation energy, this charge transfer is prohibited. A charge transit is then possible only through application of an external voltage.
The potential barrier is effective only so long as the operating temperature of the single-electron component is small enough for the thermal energy of the system to be very much less than the activation energy required for a charge transfer.
In order to make it possible for the single-electron component to be operated at technically employable temperatures, most preferably at room temperature, the energy balance dictates that the capacitance and therefore the size of the nodes must be kept as small as possible.
Conductive regions with very small dimensions, which are referred to as quantum dots, are used as nodes for producing a single-electron component in the semiconductor material. In view of the operating temperature of the single-electron component, quantum dots with dimensions of less than 10 nm are required. Conductive regions which are of a small extent in only two dimensions are referred to as quantum wires.
It has been proposed (see, for example, the publication by M. A. Reed, Spektrum der Wissenschaft 3 (1993) page 52 and J. Caro, Mictroelectronic Engineering 22 (1993) page 153) to produce small conductive regions in the semiconductor material while using gates as inversion layers. The achievable dimensions of such conductive regions depend on the form of the gates employed. It is also then possible to produce locally restricted inversion layers by using structured gates. In this case, inversion layers with dimensions in the nanometer range require gate structures in the nanometer range, which can only be produced with corresponding resolution by expensive lithography processes.
In the publication by R. Notzel et al. Adv. Mater. 5 (1993) page 22, and K. Eberl et al., Appl. Phys. Lett. 63 (1993) page 1059, it has been proposed to use GaAs/AlGaAs layers which are not grown in planar fashion. This produces lateral structuring of the conducting heterolayer during the epitaxial growth.
SUMMARY OF THE INVENTION
An object of the invention is to provide a component which is suitable as a single-electron component and comprises conductive regions whose size is not limited by the resolution of the lithography employed. A further object of the invention is to provide a production process for such a component. These and other objects of the invention are achieved by a microelectronic component, having a substrate which comprises monocrystalline silicon at least at a main face, and which comprises, at the main face, at least one surface structure having at least three faces intersecting at an intersection point which intersect in pairs on a straight intersection line, a gate dielectric which covers the surface structure at least at the intersecting faces, a gate electrode which is arranged on the surface of the gate dielectric, having at least two conductive regions, which are arranged at the main f
REFERENCES:
patent: 5313484 (1994-05-01), Arimoto
Fukui et al, "MOCVD methods for fabricating GaAs quantum wires and quantum dots", Journal of Crystal Growth 124 (1992), pp. 493-496.
Brunner et al, "Excitonic luminescence from locally grown SiGe wires and dots", Appl. Phys. Lett. 64(8), Feb. 21, 1994, pp. 994-996.
Reed, "Quantenpunkte", Spektrum der Wissenschaft, Mar. 1993, pp. 52-57.
Licharew et al, "Elektronik mit einzelnen Elektronen", Spektrum der Wissenschaft, Aug. 1992, pp.62-67.
Caro, "Quantum transport in nanostructured silicon MOSFETs", Microelectronic Engineering 22, 1993, pp.153-162, no month.
Eberl et al, "Quantum wires prepared by molecular beam epitaxy regrowth on patterned AIGaAs buffer layers", Appl. Phys. Lett. 63(8), Aug. 23, 1993, pp. 1059-1061.
Notzel et al, "Direct Synthesis of Semiconductor Quantum-Wire and Quantum-Dot Structures", Advanced Materials, 193, pp. 22-29, no month.
Eisele Ignaz
Gossner Harald
Hammerl Erwin
Risch Lothar
Crane Sara W.
Siemens Aktiengesellschaft
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