Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Patent
1995-03-31
1999-02-23
Munson, Gene M.
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
257202, 257208, 257384, 257401, 257413, H01L 2702, H01L 2978
Patent
active
058747540
ABSTRACT:
A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections. The non-rectangular configuration of the cell has compressed minimum spacings to provide a space saving that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. One or more patternable busses of conductive material are formed on a gate array structure over field oxide portions thereof during an initial step of patterning the layer of conductive material to expose active areas of differing conductivity type and to form electrodes thereover. After further processing to form other electrode regions in the active areas such as source and drain regions, but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections between various electrodes in the gate array structure so as to form a desired custom chip.
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Lee Jasopin
Padmanabhan Gobi
Yee Abraham
Yeh Stanley
LSI Logic Corporation
Munson Gene M.
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