Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2001-08-13
2003-04-22
Nguyen, Chau N. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C361S688000, C361S690000, C361S709000, C257S675000, C257S706000
Reexamination Certificate
active
06552267
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic assemblies, and more particularly to a microelectronic assembly having a stiffening member.
BACKGROUND OF THE INVENTION
A flip chip microelectronic assembly includes a direct electrical connection of face down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses face up chips with the wire connected to each pad on the chip.
The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. Flip chips are also known as “direct chip attach,” because the chip is directly attached to the substrate, board, or carrier by the conductive bumps.
The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment and services. In some cases, the elimination of old technology packages and bond wires may reduce the substrate or board area needed to secure the device by up to 25 percent, and may require far less height. Further, the weight of the flip chip can be less than 5 percent of the old technology package devices.
Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulted in the high speed off-chip interconnection.
Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips can be stacked in 3-D geometries over other flip chips or other components.
Flip chips also provided the most rugged mechanical interconnection. Flip chips when underfilled with an adhesive such as an epoxy, can withstand the most rugged durability testing. In addition to providing the most rugged mechanical interconnection, flip chips can be the lowest cost interconnection for high-volume automated production.
The bumps of the flip chip assembly serve several functions. The bumps provided an electrical conductive path from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provided part of the mechanical mounting of the chip to the substrate. A spacer is provided by the bumps that prevents electrical contact between the chip and the substrate connectors. Finally, the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
Flip chips can be combined with a variety of packages. The ball grid array is one particular package which has gained significant popularity for use with the flip chip. The ball grid array package construction is significantly different from conventional leaded packages in several ways. Typically the ball grid array uses a resin based organic substrate onto which the flip chip die and solder balls are attached. The substrate incorporates metallized trace routing for connection from the die to a second substrate, such as a system board. The connection made to the second substrate is through solder balls on the underside of the first substrate. Ball grid array packages provided numerous advantages over conventional leaded packages such as: improved electrical performance due to shorter distances between the chip and the solder balls; improved thermal performance by use of thermal vias or heat dissipation through power and ground planes incorporated into the second substrate (e.g., main PC board); using less real estate on the underlying system board or second substrate; significantly reducing handling related lead damage due to use of solder balls instead of metal leads; and when the ball grid array is reflow attached to boards, the solder balls self aligned leading to higher manufacturing yields.
Despite all of these advantages, these microelectronic assemblies are very delicate structures, the design of which and manufacturing creates difficult and unique technical problems. Continuous efforts by those working in the art are being undertaken to improve the performance, reliability and useful life of microelectronic assemblies, particularly those using flip chips. The following is a description of some of the problems facing those skilled in the art.
Typically a flip chip will be mounted and electrically connected to a supporting substrate such as a ball grid array. The substrate may be secured to a printed circuit board. The flip chip can generate a considerable amount of heat during operation which may range from about 25 to 100 watts concentrated in the area the chip which usually ranges from 1 to 4 cubic centimeters. Those working in the art are constantly seeking ways to control and manage this concentrated heat generation to avoid failure of the microelectronic device due to overheating.
Failure to manage the heat generated by the flip chip may be very costly. The heat generated from the flip chip during operation may cause the chip dimensions to change and may result in damage to signals generated by the chip. Furthermore, thermal expansion may cause the chip to curve, bend or crack. These distortions in the chip may result in damage to the electrical connections between the chip and the substrate.
Furthermore, the substrate onto which the flip chip may be mounted can be a single layer structure, or the substrate may comprise two or many more layers of materials. Often these materials tend to be quite diverse in their composition and structure. The coefficient of thermal expansion for these different layers may be considerably different and may result in uncontrolled bending or thermal induced substrate surface distortions. Such distortions can cause failure of the flip chip or other components of the substrate.
In addition to chip warpage due to thermal effects, chip or substrate warpage may be caused by other steps of the manufacturing process. For example, chip warpage may occur as a consequence of the chip underfill process. Typically, adhesive underfill is applied between the opposing faces of the chip and the underlying substrate to secure the chip to the substrate and to secure the electrical connections, usually solder joints, between the chip and the substrate. When the adhesive underfill is cured or hardened, the cured adhesive tends to shrink placing the solder joints in a compressed state, and often the shrinking adhesive causes warpage of the substrate.
In an attempt to overcome these problems, those skilled in the art have used a constraining or stiffening ring that is typically mounted to the substrate with an adhesive. The stiffening ring forms a frame around the chip with the inner perimeter of the ring being spaced from the edges of the chip. Preferably the height of the stiffening ring is greater than that of the chip. The chip may be secured to the substrate either before or after the stiffening ring is secured to the substrate.
FIG. 1
illustrates such a prior art assembly
10
using a typical stiffening ring
12
. The stiffening ring
12
is typically a block like structure with flat upper and lower surfaces
14
and
16
, and an aperture
18
through the middle thereof for receiving the flip chip
20
. The stiffening ring
12
may be secured to an underlying substrate
24
using an adhesive layer
26
. Solder bump joints
22
connect the flip chip die
20
to an underlying substrate
24
. The underlying substr
Chen Ken
Tsao Pei-Haw
Nguyen Chau N.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
Walkenhorst W. David
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