Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1999-09-30
2001-09-25
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S684000, C257S730000, C257S784000, C257S786000, C257S787000
Reexamination Certificate
active
06294830
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to microelectronic assemblies, and more specifically it relates to semiconductor chip packages.
BACKGROUND OF THE INVENTION
The semiconductor chip packaging industry is a highly competitive business in which the packaging companies are waging an ongoing battle to reduce the costs associated with packaging their own chips and, many times, the chips owned by other parties. New technologies are constantly being investigated in order to reduce the packaging cost while producing packaging structures and processes which produce similar or superior results. Further, there is on-going pressure from the electronic industry to reduce the internal impedances of semiconductor packages so that the semiconductor makers may increase the speed of their chips without experiencing significant signal degradation thereby decreasing the processing and/or response time a user of a finished electronic product will encounter when requesting the electronic product to perform a given task. Further still, the electronic industry requires that the chips are packaged in smaller and smaller form factors so that the packaged chips take up less space on a supporting circuitized substrate (such as a printed wiring board, “PWB”). It is also important that the thickness dimension of the packaged chips is reduced so that the same operational circuitry may be fit into a smaller area thereby allowing for more portability (size, weight, etc.) for the resulting finished electronic product and/or allowing for an increase in a product's processing power without also increasing its size. As the packaged chips are made smaller and placed closer and closer together on the PWB, the chips will produce more heat and will receive more heat from the adjacent chips. It is therefore also very important to provide a direct thermal path to facilitate the removal of heat from the packaged chips.
In response to industry concerns, pin grid array (“PGA”) products, in which relatively large conductive pins attach the circuitry in a particular semiconductor package to the circuitry on the PWB, and other such large packaging conventions have been used less frequently in favor of smaller packaging conventions, such as ball grid array (“BGA”) packages. In BGA packages, the aforementioned pins are typically replaced by solder balls thereby reducing the height of the packages from the PWB, reducing the area needed to package chips and further allowing for more elegant packaging solutions. The solder balls on a BGA device are generally either disposed in regular grid-like patterns, substantially covering the face surface of the packaged chip (commonly referred to as an “area array”) or in elongated rows extending parallel to and adjacent each edge of the front surface of the packaged chip.
BGA and even smaller chip scale packaging (“CSP”) technology refer to a large range of semiconductor packages which typically use interconnection processes such as wirebonding, beam lead, tape automated bonding (“TAB”) or the like as an intermediate connection step to interconnect the chip contacts to the exposed package terminals. This results in a testable device prior to mechanical attachment to the bond pads on supporting substrate. The BGA/CSP packaged chips are then typically interconnected on a PWB using standard tin-lead solder connections.
Certain packaging designs have nicely met the above stated industry concerns. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosures of which are incorporated herein by reference. In one embodiment, these patents disclose the use of a chip carrier in combination with a compliant layer to provide a cost efficient, low profile CSP.
Despite these and other efforts in the art, still further improvements in interconnection technology would be desirable.
SUMMARY OF THE INVENTION
The present inventive methods solve the aforementioned problems.
In one embodiment of the present invention, a method of making a semiconductor chip package includes the steps of first providing a sacrificial layer. A array of conductive pads or posts are next selectively formed on top of a first surface of the sacrificial layer so that a central region is defined by and is positioned between the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region so that the contact bearing (or active) surface of the chip faces away from the sacrificial layer. Typically, the chip is attached to the sacrificial layer using a thermally conductive die attach adhesive. The chip contacts are next electrically connected to respective pads using a wirebonding machine to connect a conductive wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the first surface of the sacrificial layer such that the pads, wires and semiconductor chip are all encapsulated. The encapsulant is then cured into a self-supporting form. Typically, a mold is placed on top of the first surface of the sacrificial layer prior to depositing the encapsulant so that the exterior of the package (the encapsulant) may be formed into a desired shape after the encapsulant is injected into the mold and is cured. At least a portion of the sacrificial layer is then removed to expose the bottom surface of the pads and the to provide a direct thermal path to the chip. In some embodiments, the entire sacrificial layer is removed leaving the cured encapsulant and the die attach adhesive as the bottom of the package. Many chips may be packaged simultaneously thereby allowing this process to create individual packaged chips or may be used to create multichip modules after the dicing operation which selectively separates the packaged chips.
In a further embodiment of the present invention, a dielectric polymer sheet may be disposed between the sacrificial layer and the pads such that conductive traces may interconnect the pads and thus the chips in a multichip embodiment.
In a further embodiment of the present invention, the sacrificial layer may be selectively etched on a first surface such that conductive pads protrude therefrom. The back surface of the chip is next attached between the pads in a central region defined by the pads. The chip contacts are wirebonded to respective pads and encapsulant is deposited such that it encapsulates the chip, the wires and the pads. The sacrificial layer is then etched from the exposed side so that each of the pads and the back surface of the chip may be accessed directly.
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Chambliss Alonzo
Chaudhuri Olik
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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