Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-09-20
2003-12-02
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S692000, C257S695000, C438S620000, C438S123000, C438S597000
Reexamination Certificate
active
06657286
ABSTRACT:
The present invention relates to methods of making microelectronic assemblies, and to components for use in microelectronic assemblies.
BACKGROUND OF THE INVENTION
As disclosed in certain preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266, packaged semiconductor chips desirably incorporate a semiconductor chip and flexible leads connected to the chip and extending to terminals. The terminals are movable with respect to the chip. In use, the terminals can be connected to contact pads on a circuit board or other substrate so as to connect the chip in a larger circuit. For example, the terminals may be solder-bonded to the contact pads of the substrate. Differential thermal expansion and contraction of the chip and substrate can be taken up by movement of the terminals relative to the chip. This alleviates stress on the connections between the terminals and the substrate. In certain embodiments disclosed in the aforementioned patents, the terminals are carried on a connection component such as a dielectric element. A compliant layer as, for example, a gel or an elastomer, may be disposed between the terminals and the chip, typically between the dielectric element and the chip, so as to support the terminals while leaving the terminals mechanically decoupled from the chip and free to move relative to the chip.
The connections between the chip and the terminals may be made by bending individual leads and connecting the leads to the contacts on the chip individually. As disclosed in certain preferred embodiments of commonly assigned U.S. Pat. No. 5,518,964, the disclosure of which is hereby incorporated by reference herein and a copy of which is attached hereto, numerous leads can be connected simultaneously, bent simultaneously or both. In one example of such a process, the leads and terminals are provided on a dielectric element. The leads extend along a bottom surface of the dielectric element. Each lead has a first end permanently connected to the dielectric element and a second end releasably connected to the dielectric element. By aligning the dielectric element with the chip, the second ends of all of the leads are aligned with contacts on the chip, whereupon the leads are bonded to the contacts on the chip. The bonding process may be performed so as to bond individual ends to the corresponding contacts scriatim or, preferably, so as to bond all of the second ends to the chip contacts simultaneously. After bonding the second ends of the leads, the dielectric element is moved vertically away from the chip, so as to pull the second ends of the leads away from the dielectric element and bend the leads to a vertically-extensive disposition. A fluid may be injected between the chip and the dielectric element so as to form a compliant layer between the chip and the dielectric element. In certain embodiments, the process is performed on a wafer including numerous chips disposed side-by-side. The dielectric element includes numerous regions, each associated with one chip. During the bonding step, the second ends of the leads in each region are connected to contacts on the chip associated with that region. After bonding, and typically after moving the dielectric element and chip away from one another so as to bend the leads, the wafer and the dielectric element are severed along linear severance zones referred to as “saw lanes” so as to form individual units, each including one chip and the associated region of the dielectric element, together with the terminals and flexible leads connecting the terminals to the contacts of the chip. In variants of these processes, the leads may initially be formed on the chip or wafer, rather than on the dielectric element. During assembly, the first ends of the leads are connected to conductive parts such as terminal structures or traces on the dielectric element. As disclosed, for example, in co-pending, commonly assigned U.S. patent application Ser. No. 09/317,675, the disclosure of which is hereby incorporated by reference herein, this approach is particularly advantageous where the contacts on the chip are small and closely spaced.
The processes disclosed in the '964 patent and variants thereof provide numerous advantages. In certain of these processes, the vertical movement of the dielectric element and chip displaces the first end of each lead away from the second end of the lead. This tends to stretch the leads, which would leave the leads taut in the finished assembly. It is desirable to leave some slack in the leads in the finished assembly. As disclosed in the '964 patent, two fundamental approaches have been employed to compensate for this phenomenon and provide slack in the leads. In the first such approach, sometimes referred to as “lift and shift,” the dielectric element and the chip or wafer are moved horizontally relative to one another, typically at the same time as they are moved vertically away from one another. The direction of the horizontal movement is selected so that it displaces the first ends of the leads horizontally toward the second ends of the leads. Desirably, the horizontal displacement provides at least enough slack in each lead to compensate for the extension induced by the vertical displacement. In another approach, the leads are initially curved in the horizontal plane. The vertical movement causes some reduction in this curvature, but preferably does not pull the leads fully taut. Either approach can provide satisfactory compensation for the lead elongation caused by the vertical movement.
These processes can be used with chips having an “area array” contact pattern in which the contacts of the chip are substantially evenly spaced over all or most of the chip front surface, or with chips having contacts disposed in rows on a small portion of the chip front surface. Many chips have all or most of their contacts disposed in rows adjacent the edges of the chip. For example, where the chip has the conventional rectangular shape, the contacts may be disposed in rows along all four edges of the front surface, or along two opposite edges. The contacts within each row typically are disposed at small center-to-center distances or “contact pitch.” As disclosed, for example, in certain embodiments of U.S. Pat. No. 5,830,782, the disclosure of which is hereby incorporated by reference herein and a copy of which is annexed hereto, leads which are initially curved prior to connection with the chip can be used. However, in some cases it would be desirable to use leads, which are initially straight with such a chip, so as to facilitate the bonding process.
SUMMARY OF THE INVENTION
A method of making a microelectronic unit according to one aspect of the invention most preferably includes the step providing first and second elements and leads extending between said elements, each said lead having a first end connected to the first element and a second end connected to the second element. The leads may be provided on either one of the elements and connected to the opposite element when the elements are united during the process. For example, when the first element is a connection component incorporating a dielectric element and the second element is a chip, assembly of chips or a wafer, the leads may be carried on the dielectric element or on the chips or wafer prior to assembly. The directions of the leads can be described with reference to a “direction vector.” Each lead has a direction vector from its first end (the end connected to the first element) to its second end (the end connected to the second element). In processes according to this aspect of the invention, at least some of the direction vectors are non-parallel to others of said direction vectors. However, the direction vectors have components in a common horizontal direction. For example, the leads may be provided in rows including a first row extending in X horizontal directions and a second row extending in Y horizontal directions perpendicular to the X directions. The direction vectors of leads in the first row having compo
Everhart Caridad
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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