Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-09-28
2003-01-21
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S758000, C438S619000, C438S780000, C438S781000, C438S623000
Reexamination Certificate
active
06509623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to microelectronic structures. More particularly, the present invention relates to microelectronic air-gap regions.
2. Related Art
Integrated circuits often include multiple devices formed within a substrate and multiple levels of interconnect which connect the devices to form functional circuits. Device size and interconnect feature size and spacing generally affect manufacturing costs and performance of the integrated circuits. For example, manufacturing costs per chip may be reduced by reducing device and interconnect feature size and spacing. In particular, as the feature size and spacing are reduced, smaller chips can be fabricated for the same circuit and each semiconductor wafer can yield more chips. In addition, device performance generally improves as device feature size is reduced. For example, device speed increases and power consumption decreases as the device feature size decreases. Accordingly, circuits having relatively small devices are generally desirable.
Unfortunately, reducing interconnect feature size and spacing may deleteriously affect circuit performance. For example, as the separation between interconnect features decreases, the circuit becomes increasingly affected by capacitance coupling between two or more interconnect features separated by a dielectric material. Furthermore, as interconnect feature size decreases, the resistance of the feature generally increases (e.g., line resistance increases). As a result, the circuits become increasingly susceptible to crosstalk and to resistance-capacitance (“RC”) delays as the capacitance coupling between interconnect features and interconnect line resistance increase.
Generally, the capacitance of two or more conductive features is proportional to the dielectric constant of a material separating the features and inversely proportional to the distance between the features. Consequently, the capacitance coupling of features increases as the distance between the features decreases and as the dielectric constant of material between the features increases. Adverse affects of reduced spacing between interconnect features may be mitigated by interposing material having a low dielectric constant (low-k) material between the interconnect features.
Typical dielectric material used in the manufacture of integrated circuits such as silicon oxide (SiOx) has a dielectric constant of about 4. However, interconnect structures have recently been developed which use air, having a dielectric constant of about 1, between adjacent interconnect lines within a metallization level.
Although these conventional air-gap structures overcome some of the problems associated with use of higher dielectric constant materials, circuits employing such air-gap structures may incur other problems. The conventional gap structures are typically fabricated by forming air-gaps between metal lines by depositing material conformally over the metal lines (i.e., by intentionally poor-filling the gaps between the metal lines when depositing dielectric materials used for isolation and mechanical support of the next interconnect metal layer). Thus, the number and location of the air-gap s is often determined by the interconnect layout, often resulting in extensive use of air-gap structures, which tend to weaken the structure of the circuit. In addition, air-gap regions do not conduct heat well. Thus, circuits including conventional air-gap structures tend to readily heat compared to circuits employing more conventional dielectric regions. As the circuit temperature increases, the devices and interconnect structures within the circuit become susceptible to reliability problems such as undesired diffusion of materials within the device and the interconnect. Accordingly, improved circuits having air-gap structures only at critical locations to improve performance that are mechanically strong and less susceptible to heat buildup are desired.
In addition to the problems set forth above, circuits including conventional air-gap dielectric structures may be susceptible to poisoned via problems caused by misalignment of the via plugs to underlying metal lines. Filling the mis-aligned via holes, which are connected to the air-gap due to the misalignment with the underlying metal lines, is often difficult, resulting in relatively poor contact between interconnect layers. Accordingly, improved circuits which are less susceptible to poisoned vias and methods of forming the circuits are also desired.
U.S. Pat. No. 5,342,683, issued to Fitch et al. on Jun. 28, 1994, discloses methods of forming an air-gap between two conductive features within a metallization level. One method disclosed in the Fitch et al. patent includes forming an air-dielectric region by forming sacrificial spacers within a trench, forming a pillar between the spacers, removing the spacers to form air regions, and sealing the air regions. This method results in a dielectric structure including a pillar surrounded by one or more air-gap regions. Because the dielectric constant of the pillar is generally higher than the dielectric constant of air, the resultant dielectric constant of the dielectric structure formed according to this method is higher than a structure including only air.
The Fitch et al. patent also discloses methods of forming air-gap regions using selective growth techniques. Such methods may be relatively complex and generally require additional selective growth processing steps to form a seal over the air-gap region. These additional process steps in the manufacture of microelectronic devices are undesirable because such steps typically increase the cost of the circuit and a probability that the circuits will include a defect. Accordingly, improved microelectronic circuits having air-gap dielectric regions of lower effective dielectric constant and methods to robustly and easily seal the air-gap regions are desired.
Air-gap structures may also suitably be desirable for other microelectronic structures. For example, micro electromechanical systems (“MEMS”) often include air-gap regions, which define micro-mechanical structures within the MEMS. Accordingly, methods of forming air-gap structures suitable for facilitating formation of micro-mechanical structures are also desired.
SUMMARY
The present invention provides an improved microelectronic structure and method for forming the structure. More particularly, the present invention provides an improved air-gap region suitable for microelectronic structures and/or micro-mechanical structures and a method of forming the same.
The way in which the present invention addresses the drawbacks of the now-known air-gap structures and methods of forming the structures is discussed in greater detail below. In general, the invention provides improved air-gap dielectric regions which are formed using a new fabrication method which is easy to implement in manufacturing.
In accordance with an exemplary embodiment of the present invention, an air-gap dielectric structure is formed by forming a pattern of conductive or dielectric features—e.g., a pattern of interconnect lines—on a substrate, depositing a material over the patterned features and the substrate, removing any excess material if necessary, forming an etch mask having apertures configured to allow removal of the deposited material, removing the deposited material between at least some of the patterned features, and forming a seal over the apertures of the etch mask to form an air-gap region. Use of an etch mask allows relatively easy and reliable sealing of air-gap regions and provides a robust planar surface for subsequent processing. In accordance with one aspect of this embodiment, the etch mask may be patterned to allow formation of the air-gap structures only in desired areas between the patterned features on the substrate. For example, the air-gap structures may suitably be formed only between closely-spaced features or only between some of the closely spaced features, leaving solid material
Farjami & Farjami LLP
Newport Fab LLC
Smith Matthew
Yevsikov V.
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