Microdisplay pixel cell and method of making it

Details Microdisplay pixel cell and method of making it Microdisplay pixel cell and method of making it

2003-11-05

2004-12-28

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Including integrally formed optical element

C438S029000, C438S151000, C438S155000

Reexamination Certificate

active

06835584

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a microdisplay pixel cell and method of making it, and more particularly, to a pixel cell with a metal-insulator-metal (MIM) capacitor.
2. Description of the Prior Art
In modern planar display technology, plasma display panel (PDP) and liquid crystal display (LCD) are two main streams. They both constitute numerous display grids called as pixel cells. The former one is applied in a large-sized market and still has a gap from widespread application since the technique for mass production is not broken through yet and cost is high. A thin-film transistor LCD (TFT LCD), which is prevailing in recent years, is a representative of the latter one and is mainly applied in the market smaller than 17 inches. During the fabrication of the TFT LCD products, however, defects such as dots or lines may occur to the LCD. Thus, compensate techniques are required to improve the production yields.
A microdisplay utilizes a silicon chip as a substrate and utilizes a standard CMOS process to form pixel cell matrices, integrated drivers and other electronic devices on the silicon chip. An advantage of the microdisplay is to utilize the CMOS process, since the CMOS process is well developed at the present semiconductor industry. As a result, high stability and reliability can be achieved when compared to the LCD. In addition, using this process, each pixel pitch can be shrank to less than 10 &mgr;m, therefore a high resolutions is obtained. When compared to the PDP, the microdisplay not only has an absolute superiority in cost but also has intrinsic advantages of the microdisplay. In addition, being assisted with adequate projection techniques, the microdisplay can further be applied in markets for large-sized displays. Therefore, a liquid crystal on silicon (LCOS) display, a kind of the microdisplays, attracts many major manufacturers to devote themselves in developing and is the display with highest potentiality.
Please refer to
FIG. 1
of a layout of the prior art LCOS display pixel cell
10
. The prior art LCOS display pixel cell
10
constitutes a transistor block
18
, two pixel cap top plates
20
and one pixel cap bottom plate
22
disposed at either side of the transistor block
18
. The pixel cap top plates
20
and the pixel cap bottom plate
22
form a pixel capacitor.
The transistor block
18
comprises four transistors
16
. In other words, the transistor block
18
comprises two polysilicon gates
12
electrically connecting to a word line (not shown). Each polysilicon gate
12
crosses two active areas
14
. One drain contact plug a is formed in each active area
14
for electrically connecting to a video data line (not shown), and two source contact plugs b are formed in each active area
14
for electrically connecting to a pixel cap top plate
20
respectively. One row select contact plug c is formed on top of each polysilicon gate
12
for electrically connecting to a row select line, which is the above-mentioned word line. Moreover, one contact plug d and one contact plug e are formed, respectively, on top of the pixel cap top plate
20
and the pixel cap bottom plate
22
for electrically connecting to the source contact plug b and ground.
Please refer to
FIG. 2
to
FIG. 7
of schematic diagrams of a method for forming the prior art liquid crystal on silicon (LCOS) display pixel cell
72
.
FIG. 2
to
FIG. 7
are cross-sectional diagrams along line A-A″ shown in FIG.
1
. As shown in
FIG. 2
, the prior art LCOS display pixel cell
72
is made on a semiconductor wafer
30
. The semiconductor wafer
30
comprises a P-type silicon substrate
32
. A plurality of isolators
34
are disposed on the surface of the P-type silicon substrate
32
for defining an active area for each device. The isolator
34
is usually a field oxide layer formed by a local oxidation (LOCOS) or a shallow trench isolation (STI).
AS shown in
FIG. 3
, a cleaning process is performed followed by homogeneously depositing a first polysilicon layer
36
on the P-type silicon substrate
32
utilizing a low pressure chemical vapor deposition (LPCVD) process. In the LPCVD process, silane (SiH
4
) is utilized as a reactive gas, a temperature is controlled in a range from 575° C. to 650° C., and a pressure is in a range from 0.3 to 0.6 torr.
Then as shown in
FIG. 4
, a first photoresist layer
38
is coated on the surface of the first polysilicon layer
36
followed by performing a first photolithography process to define two pixel cap bottom plate patterns
41
in the first photoresist layer
38
. Thereafter a dry etch process is performed to vertically remove the first polysilicon layer
36
along the defined pixel cap bottom plate patterns
41
until reaching the surface of the isolator
34
, so two pixel cap bottom plates
42
are formed. Following this, the first photoresist layer
38
is removed.
As shown in
FIG. 5
, a thermal oxidation is utilizeed to simultaneously form a gate oxide layer
44
composed of silicon dioxide (SiO
2
) on the surface of the active area
14
and simultaneously form a capacitor dielectric layer
45
on the surface of two pixel cap bottom plates
42
. Then, a LPCVD process is performed to form a second polysilicon layer
46
on the surface of the P-type substrate
32
to cover the two pixel cap bottom plates
42
.
Thereafter as shown in
FIG. 6
, a second photoresist layer
48
is formed on the surface of the second polysilicon layer
46
. A second photolithography process is performed to define a gate pattern
49
and two pixel cap top plate patterns
51
in the second photoresist layer
48
. Then, an anisotropic dry etch process is performed to remove the second polysilicon layer
46
not covered by the second photoresist layer
48
until reaching the surface of the gate oxide layer
44
and the capacitor dielectric layer
45
, thus simultaneously form a transistor gate
52
and a pixel cap top plate
54
. Finally, the second photoresist layer
48
is removed. The top plate
54
, the bottom plate
42
and the capacitor dielectric layer
45
form a complete pixel capacitor
58
.
As shown in
FIG. 7
, a third photoresist layer (not shown) is then formed and an ion implantation process is utilized to form a source/drain (S/D)
63
and
64
in the P-type substrate
32
at either side of the transistor gate
52
. Thereafter, a dielectric layer
66
is formed on the P-type substrate
32
. After that a photo-etching-process (PEP) is performed to form a plurality of contact holes
68
reaching the surface of the gate
52
in the dielectric layer
66
, functioning as a row select contact plug c as shown in
FIG. 1
to electrically connect to a subsequent formed row select line. After forming the contact holes
68
, a chemical mechanical polishing process (CMP) is performed to the dielectric layer
66
to improve the planarization of the dielectric layer
66
and decrease the difficulty of a subsequent photo-etching-process for forming other contact holes.
Finally, back end processes, such as contact plug processes and metal interconnects processes are performed, respectively, to form the row select line, the inter-metal dielectric (IMD), the drain contact plug a, the source contact plug b, the contact plug d, the contact plug e and the video data line to complete the LCOS display pixel cell
72
.
Since the pixel capacitor is located at either side of the transistor and occupies the same plane as the transistor according to the prior art design, this design cause a considerable limitation to chip size shrinkage. In addition, noise of the device cannot be effectively reduced because the length of each metal line in the device cannot be shortened. Moreover, since both the pixel cap top plate and the pixel cap bottom plate are composed of polysilicon, mismatch and residue problems tend to occur due to the effect of nonuniformity between the etching process and process parameter, such as stop layer. This results in deviations from the designed electrical performance of the capacitor.
To improve the

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