Microdisplay and interface on single chip

Details Microdisplay and interface on single chip Microdisplay and interface on single chip

2007-10-16

2007-10-16

Osorio, Ricardo (Department: 2629)

Computer graphics processing and selective visual display system

Plural physical display element control system

Optical means interposed in viewing path

C345S204000

Reexamination Certificate

active

10831545

ABSTRACT:
A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same to field sequential color signals for generation of full color images. It includes column data processors having a comparator for each block of N-columns of pixels. Image data is double-buffered in SRAM memory cells located beneath the pixel electrodes, but not within each pixel. The stored data is logically associated with each pixel via the column data processors. Image compression is accomplished by converting RGB data to a variant of YUV data and sampling the color components of the converted data less frequently than the luminance components. The SRAM image buffer consumes a reduced amount of power. A temperature compensation scheme allows the temperature of the microdisplay to be sensed and the drive voltage to the pixel electrodes to be varied in response thereto.

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