Boots – shoes – and leggings
Patent
1985-07-03
1988-12-27
Chan, Eddie P.
Boots, shoes, and leggings
G06F 0946
Patent
active
047945265
DESCRIPTION:
BRIEF SUMMARY
The invention relates to microcomputers and particularly to scheduling a plurality of concurrent processes to be executed by a microcomputer.
BACKGROUND OF THE INVENTION
Our European Patent Specification No. 0113516 describes a microcomputer for executing a plurality of concurrent processes. It provides for scheduling and descheduling processes by use of a link list. It further provides synchronised message communication between processes. The scheduling means is arranged to schedule or deschedule processes to permit message communication to take place when processes are at corresponding stages in their program sequences. In that example all processes are treated as having the same priority.
OBJECTS OF THE INVENTION
It is an object of the present invention to provide an improved microcomputer which allows allocation of different priorities to different processes.
It is a further object of the present invention to provide a microcomputer in which processes awaiting execution may be grouped according to their priority.
SUMMARY OF THE INVENTION
The present invention provides a new method and apparatus for scheduling processes in a computing system. Each process has a priority assigned to it and illustratively this information can comprise data in a "process descriptor." For example, there may be processes having first priority and other processes having second priority. Processes, regardless of their assigned priority, may be scheduled for execution or not. The processes having first priority and which are scheduled for execution are arranged to form a first linked list. Second priority processes scheduled for execution are arranged to form a second linked list. If there is a third level of priority, scheduled processes having that priority would form a third linked list, and so on until all of the differing priorities are accommodated.
Preferably the linked list is formed using workspaces. In a preferred aspect of this invention, each process has associated with it a workspace consisting of addressable memory locations. Preferably a pointer, called a workspace pointer, identifies a reference location within the workpiece for a process. In this manner, processes can be identified by their corresponding workspace pointers. At a prescribed or known location within the process workspace is a memory location used for storing a pointer to the next process (workspace) on the linked list of the same priority. Thus, if there are three processes having first priority, then there will be three work spaces. At a known location in the first workpiece will be found a pointer or other indicator for the next process on the first linked list. Likewise, in the workspace for the second process of that priority at the known location will be found a pointer or other indicator of the third process on the first linked list. In this fashion, the first linked list identifies processes having a given priority level and which are scheduled for execution by the processor. Similarly, the second liked list has the same characteristics, as do other linked linked lists, if any.
The computer according to the present invention includes several registers. Preferably, there is a first bank of registers corresponding to first priority processes and a second register bank corresponding to second priority processes. The register bank or banks include a storage means such as a register used for temporary storage of the work space pointer (or other indicator) for the process which is currently being executed by the processor. Such process accordingly is denominated as the "current process." Preferably, each register bank will include a respective workspace pointer register.
Preferably, the bank or banks of registers also include another storage device such as a second register for temporarily storing the workspace pointer or other indicator of the process which is the next one scheduled for execution. Where there are two or more register banks corresponding to first and second priority processes, the second register in the first bank store
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patent: 4084228 (1978-04-01), Dufond et al.
patent: 4172284 (1979-10-01), Heinrich et al.
patent: 4318173 (1982-03-01), Freedman et al.
patent: 4387427 (1983-06-01), Cox et al.
"Some Experiences of Implementing the Add Concurrency Facilities On a Distributed Multiprocessor Computer System" written by Shoja et al., Software & Microsystems, vol. 1, No. 6, Oct. 1982, pp. 147-152.
May Michael D.
Shepherd Roger M.
Chan Eddie P.
Inmos Limited
Manzo Edward D.
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