Microcomputer with multiple CPU'S on a single chip with provisio

Details Microcomputer with multiple CPU'S on a single chip with provisio Microcomputer with multiple CPU'S on a single chip with provisio

1994-05-31

1996-10-15

Harvey, Jack B.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

39542103, 395800, 377 39, G06F 1300

Patent

active

055663036

ABSTRACT:
A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.

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David Jones, "Fehlertoleranz und Zuverlassigkeit in Mikroprozessor-Systemen", Elektronik 24/1990, pp. 54-60.

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