Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-03-03
2002-07-02
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C712S010000, C712S011000, C712S014000
Reexamination Certificate
active
06414368
ABSTRACT:
BACKGROUND OF THE INVENTION
Microcomputers generally comprise a processor and memory and may operate in accordance with a sequence of instructions derived form a stored program. The instructions may include a so-called “function” selected from a set of selectable functions and which define the operation which is carried out by the processor in response to that instruction. Processors may wish to communicate with external peripheral equipment including other microcomputers. For this reason, microcomputers are sometimes connected into a network with peripheral equipment or a plurality of microcomputers. This has generally been done through output ports or pins on the microcomputer and commonly these ports or pins have needed programming in order to communicate between processes on different microcomputers. Furthermore, it is conventional in microcomputers for communications, including the external communications, to occur through a bus which provides a bottleneck reducing the speed of operation of the microcomputer.
Consequently conventional microcomputers have not provided satisfactory building blocks for use in extended networks of microcomputers. Networks have generally caused loss of speed of operation and needed additional interface hardware.
OBJECTS OF THE PRESENT INVENTION
It is an object of the present invention to provide an improved microcomputer which is usable as a building block for a network of microcomputers.
It is a further object of the present invention to provide a network of interconnected microcomputers in which the network operates in the same manner as each individual microcomputer.
It is a further object of the invention to provide an improved microcomputer with a plurality of communication links which can operate concurrently.
It is a further object of the present invention to provide an improved microcomputer which may communicate with other microcomputers through links which avoid time delays normally encountered in shared buses.
It is a further object of the present invention to provide an improved microcomputer having a plurality of serial links thereby enabling it to be connected in communication with a larger number of other microcomputers.
It is a further object of the present invention to provide a microcomputer with independent serial links which allow direct connection with other microcomputers allowing operation of communication channels through the separate serial links concurrently.
SUMMARY OF THE PRESENT INVENTION
The present invention provides a microcomputer comprising an integrated circuit device having a processor and memory in the form of RAM on the same integrated circuit device, and a plurality of communication links each including a register for storing a plurality of data bits and each arranged to provide a communication path for sole connection to a similar link of a further microcomputer whereby each microcomputer forms a building block in a network of microcomputers.
The present invention also provides a network of interconnected microcomputers each comprising a processor and memory in the form of RAM on a single integrated circuit device, each microcomputer having a plurality of communication links each interconnected by connecting means with another microcomputer in the network, said link each forming part of a point to point connection which solely interconnects a respective pair of microcomputers and is not shared with any other microcomputer or memory, said links each including at least one register for holding a plurality of bits of data to be transmitted or received through the link.
The present invention also provides a microcomputer including on the same integrated circuit device memory in the form of RAM and a processor, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a required function to be executed by the processor, the function being one of a set of selectable functions, wherein:
(a) the microcomputer includes a plurality of communication links each arranged to provide a communication path for sole connection to a corresponding link of a further microcomputer, said communication links each including a register for storing a plurality of data bits for transmission through the communication link and temporary store means for receiving pointer values indicating the state of the link for use in synchronising message transmission through the link, and
(b) said processor includes:
(i) a plurality of registers and data transfer means for use on data transfers to and from said registers
(ii) means for receiving each instruction and loading into one of the process registers a value corresponding to the function bits of the instruction, and
(iii) control means for controlling said data transfer means and registers and arranged to respond to said function bits to cause the processor to operate in accordance with said function bits, the function set including one or more functions which cause said control means to load into the temporary store of the communication links pointer values for use in synchronising message transmission through the communication links.
A network of microcomputers as aforesaid may be linked together by connections between respective communication links, each connection between two microcomputers comprising two unidirectional point to point connections providing respectively input and output paths for each microcomputer. In this way, an extended network may be formed by simple wire connections between output pins and input pins on respective microcomputers. No special interface is needed.
Preferably each communication link includes-control logic arranged to cause transmission of data from a said register in an output channel of a communication link and to detect receipt of data in a said register of an input channel of a link, whereby communication between microcomputers may be effected concurrently through a plurality of links.
Preferably said control logic is arranged to respond to the state of registers in both input and output channels of each link and to cause transmission from an output channel of a data string and includes means for generating and detecting special values indicating the beginning and end of the string and means to cause an output channel to transmit an acknowledgment signal when the input channel of the same link has received the said special value representing the end of a data string.
Preferably the control logic is arranged to permit data transfers between the registers of a pair of links independently of the processor, thereby permitting message transmission concurrently with process execution by the processor.
Preferably the memory of the microcomputer provides one or more communication channels for message transmission between processes executed on the same microcomputer, each channel having at least one word location arranged to receive a pointer value for use in synchronising message transmission between the said processes, the said control means being arranged to respond to a selected function from the function set to locate a pointer in said word location indicating the state of the channel for use in synchronising message transmission. Preferably said processor includes means for providing pointer values each indicating a respective process which is executed by the microcomputer, said control means being arranged to respond to functions in the function set to load into said register of the communication link a pointer indicating a particular process that is waiting to communicate through said channel together with means for loading into said register a special pointer to indicate that no process is waiting to communicate through that channel.
The invention also provides a method of communication of data between processes in an array of computers each comprising an integrated circuit device having a processor, memory and a plurality of communication links, comprising est
Edwards Jonathan
May Michael David
Waller David L.
Chaudhuri Olik
Ha Nathan W.
Jorgenson Lisa K.
Kubida William J.
STMicroelectronics Limited
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