Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-24
2001-01-23
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S020000
Reexamination Certificate
active
06177821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer with a frequency multiplication circuit to generate and supply a clock signal of a desired frequency obtained by multiplying a clock signal of a predetermined frequency supplied from an external device.
2. Description of the Related Art
FIG. 1
is a block diagram showing a configuration of a conventional microcomputer with a frequency multiplication circuit. In
FIG. 1
, the reference number
1000
designates the microcomputer,
1002
denotes a central processing unit (hereinafter referred to as CPU), and
1003
indicates a ROM in which a program to execute the microcomputer
1000
and data are stored. The reference number
1004
designates a RAM to temporarily store data. Further, the reference number
1005
denotes a peripheral circuit such as a timer, and
1006
indicates an interrupt circuit for processing interrupt requests transferred from the peripheral circuit
1005
and other circuits. The reference number
1007
designates a Phase Locked Loop (PLL) as a frequency multiplication circuit for generating a clock signal of a frequency obtained by multiplying a clock signal
1012
supplied through an external terminal
1010
. The reference number
1008
denotes a clock generation circuit for generating a standard clock signal to be used for operating a microcomputer based on the XIN signal
1012
supplied through the external
1010
and the clock signal
1013
outputted from the frequency multiplication circuit
1007
. The reference number
1009
denotes an interface circuit through which data and addresses are transferred between the microcomputer
1000
and external devices. The reference number
1011
designates internal address buses and internal data buses in the microcomputer
1000
. Thus, the conventional microcomputer with the frequency multiplication circuit comprises the circuit elements
1002
to
1011
and operates based on the various control signals
1012
to
1015
described above.
Next, a description will be given of the operation of the conventional microcomputer with the frequency multiplication circuit.
The frequency multiplication circuit
1007
incorporated in the microcomputer
1000
shown in
FIG. 1
is a circuit as a phase locked loop type. Hereinafter the frequency multiplication circuit
1007
will be referred to as the PLL.
Firstly, the configuration and operation of the PLL
1007
incorporated in the conventional microcomputer
1000
will be explained.
FIG. 2
is a block diagram showing a configuration of the PLL
1007
. In
FIG. 2
, the reference number
1016
designates a phase frequency comparison device (PFD) for comparing the phases of the frequencies of two kinds of input signals, the XIN input signal and the clock signal CLK oscillated in the PLL
1007
. The reference number
1017
denotes a charge pump (CP),
1018
indicates a voltage control oscillator (VCO) for changing the frequency oscillated based on a VCONT input voltage
1028
transferred from the charge pump
1017
. The voltage control oscillator
1018
generates a high frequency when the VCONT input voltage
1028
is high and a low frequency when it is low. The reference number
1019
designates a division circuit for dividing the clock signal outputted from the VCO
1018
by a desired multiplication rate. For example, the frequency of the clock signal is divided by two when the desired multiplication rate is two, and the frequency of the clock signal is divided by three when the desired multiplication rate is three. The reference number
1020
designates a resistance, and
1021
denotes a capacitor. A low pass filter comprises the resistance
1020
and the capacitor
1021
.
Next, the operation of the PLL
1007
will be explained when the multiplication rate is two.
When the power switch of the microcomputer
1000
shown in
FIG. 1
enters ON, the microcomputer
1000
inputs the XIN input signal. In this situation, the VCO
1018
in the PLL
1007
shown in
FIG. 2
initiates the oscillation of the frequency with a constant frequency. The clock signal
1023
generated by and outputted from the VCO
1018
is divided by two by the division circuit
1019
. The divided clock signal
1024
is outputted from the division circuit
1019
to the PFD
1016
. Thereby, the PFD
1016
compares a rising time of the XIN input signal
1012
with a rising time of the clock signal
1024
.
In a case that there is a phase difference of the rising time between them shown in
FIG. 3
, that is to say, when the rising time of the XIN input signal
1012
is faster than that of the clock signal
1024
(Timing T
121
), the PFD
1016
judges that the frequency of the clock signal
1024
is delayed from the XIN input signal
1012
and changes the level of the XINFAST signal
1025
from a high level (H level) to a low level (L level) at the rising time (Timing T
121
) of the XIN input signal
1012
.
After this, the level of the XINFAST signal
1025
is changed from the L level to the H level when the PFD
1016
inputs the rising edge of the clock signal
1024
(Timing T
122
). The PFD
1016
then outputs to the charge pump (CP)
1017
the phase difference between the rising edge of the XIN input signal
1012
and the rising edge of the clock signal
1024
as the XINFAST signal
1025
of a low pulse (L pulse). During the above operation, the level of the PLLFAST signal
1026
keeps the H level.
During the input of the XINFAST signal
1025
of the L pulse, the CP
1017
outputs the data of the H level. Thereby, the capacitor
1021
in the low pass filter
1022
is charged and voltage potential of the VCONT voltage
1028
is increased by the electric charge. This operation increases the frequency of the clock signal
1023
oscillated by and outputted from the VCO
1018
.
On the contrary, as shown in
FIG. 4
, when the rising time of the clock signal
1024
is faster than that of the XIN input signal
1012
(Timing T
131
), the PFD
1016
judges that the frequency of the clock signal
1024
is faster than the frequency of the XIN input signal
1012
, and changes the level of the PLLFAST signal
1026
from the H level to the L level at the rising time (Timing T
131
) of the clock signal
1024
.
After this, the level of the PLLFAST signal
1026
is changed from the L level to the H level when the PFD
1016
inputs the rising edge of the XIN input signal
1012
(Timing T
132
). The PFD
1016
then outputs to the charge pump (CP)
1017
the phase difference between the rising edge of the clock signal
1024
and the rising edge of the XIN input signal
1012
as the PLLFAST signal
1026
of a low pulse (L pulse). During the above operation, the level of the XINFAST signal
1025
keeps the H level. During the input of the PLLFAST signal
1026
of the L pulse, the CP
1017
outputs the data of the L level. Thereby, the capacitor
1021
in the low pass filter
1022
is discharged and voltage potential of the VCONT voltage
1028
is decreased by the electric charge. This operation decreases the frequency of the clock signal
1023
oscillated by and outputted from the VCO
1018
.
By repeating those two operations described above, when the rising edges of the XIN input signal
1012
and the clock signal
1024
, that is to say, both frequencies become a same value, as shown in
FIG. 5
, the XINFAST signal
1025
and the PLLFAST signal
1026
keep the H level. Thereby, the VCO
1018
may output the clock signal
1023
of a constant voltage by the low pass filter
1022
when both rising edges of them become same. That is to say, the VCO
1018
outputs the clock signal having the stable frequency multiplied by two.
Because the conventional microcomputer with the frequency multiplication circuit has the configuration described above, it takes a long time that the PLL
1007
outputs a stable clock signal of a desired frequency after the power of the microcomputer
1000
enters ON and the XIN input signal is then supplied to the PLL
1007
. The time required to output the stable clock signal of the desired frequency fluctuates by
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Zweizig Jeffrey
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