Microcomputer with automatic refresh of on-chip dynamic RAM tran

Details Microcomputer with automatic refresh of on-chip dynamic RAM tran Microcomputer with automatic refresh of on-chip dynamic RAM tran

1981-04-13

1984-07-10

Zache, Raulfe B.

Boots, shoes, and leggings

365222, G06F 1300

Patent

active

044596600

ABSTRACT:
A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.

REFERENCES:
patent: 4332008 (1982-05-01), Shima et al.
Glaise, R., "Quasi-Transparent Refresh Mechanism for Dynamic Memories in Microprocessor Environment," IBM T.D.B., vol. 22, No. 3, Aug. 1979, pp. 1037-1038.

Affiliated with

Also associated with

Rating

Microcomputer with automatic refresh of on-chip dynamic RAM tran does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microcomputer with automatic refresh of on-chip dynamic RAM tran, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer with automatic refresh of on-chip dynamic RAM tran will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1579610