Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-09-25
2001-04-17
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S182000, C348S569000, C348S563000
Reexamination Certificate
active
06219072
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a microcomputer with a built in character display circuit (hereinafter called the OSD (onscreen display) circuit) for displaying character information on a display screen, and to a visual display unit that employs such a microcomputer.
In order to achieve improvements in device operability and to display various information, AV (audio/video) devices, such as television receivers and video cassette recorders, contain a microcomputer with an OSD capability to display character information on a display screen (e.g., a CRT display and an LCD (liquid crystal display)).
A typical conventional microcomputer with a built in OSD circuit is described. Generally, such a conventional microcomputer comprises a CPU (central processing unit) for executing instructions, a ROM (read only memory) for storing CPU instructions, a RAM (random access memory) which stores CPU data or serves as a stack region, an OSD circuit for displaying character information on a display screen, a ROM for storing font data of characters, and a RAM for storing character information including (i) character codes representing the characters and (ii) attribute data of the characters such as character size data and character color data. In such a conventional microcomputer architecture, the CPU requires its own ROM and RAM while the OSD circuit also requires its own ROM and RAM. This results in an increase in chip area. Another problem is that since ROMs and RAMs necessary for CPUs are different in storage capacity from ROMs and RAMs necessary for OSD circuits with respect to the grade of AV devices, to the destination thereof, and to required OSD capabilities, numerous types of products are required to be prepared when trying to achieve an optimal design according to various specifications.
SUMMARY OF THE INVENTION
The present invention was made to provide solutions to the above-described problems. Accordingly, an object of the present invention is to provide a microcomputer with a built in OSD circuit capable of achieving a reduction in chip area and of being designed readily and optimally with respect to various specifications. Another object of the present invention is to provide a visual display unit that employs a microcomputer of the present invention.
The present invention discloses a first microcomputer architecture. The first microcomputer architecture of the present invention comprises (a) a central processing unit (CPU) for instruction execution, (b) an on-screen display (OSD) circuit for display of character information on a display screen, (c) a read only memory (ROM) which is arbitrarily divided into a first ROM storage space for use by the CPU and a second ROM storage space for use by the OSD circuit, (d) a random access memory (RAM) which is arbitrarily divided into a first RAM storage space for use by the CPU and a second RAM storage space for use by the OSD circuit, (e) a common bus which is made up of a data bus and an address bus and to which the CPU, the OSD circuit, the ROM, and the RAM are connected in such a way as to allow the CPU and the OSD circuit to acquire an exclusive right to use the ROM and the RAM, and (f) a bus liberation signal line over which when the common bus is not in use by the CPU, a message that the common bus is made available to the OSD circuit is sent to the OSD circuit from the CPU.
Aspects of the first microcomputer architecture of the present invention are discussed. In accordance with the first microcomputer architecture of the present invention, the ROM is divided into two storage spaces, namely the first ROM storage space (which is used by the CPU) and the second ROM storage space (which is used by the OSD circuit), and the RAM is likewise divided into two storage spaces, namely the first RAM storage space (which is used by the CPU) and the second RAM storage space (which is used by the OSD circuit). Such ROM and RAM storage space division makes it possible to meet various specifications. The CPU and the OSD circuit can access the ROM and the RAM in a time-sharing manner. When the OSD circuit is notified of the fact from the CPU that the common bus is available to the OSD circuit, the OSD circuit is made able to immediately access the ROM or the RAM.
The present invention discloses a second microcomputer architecture. The second microcomputer architecture of the present invention comprises (a) a central processing unit (CPU) for instruction execution, (b) an on-screen display (OSD) circuit for display of character information on a display screen, (c) a read only memory (ROM) which is arbitrarily divided into a first ROM storage space for use by the CPU and a second ROM storage space for use by the OSD circuit, (d) a random access memory (RAM) which is arbitrarily divided into a first RAM storage space for use by the CPU and a second RAM storage space for use by the OSD circuit, (e) a first common bus which is made up of a data bus and an address bus and to which the CPU, the OSD circuit, and the ROM are connected in such a way as to allow the CPU and the OSD circuit to acquire an exclusive right to use the ROM, (f) a second common bus which is made up of a data bus and an address bus and to which the CPU, the OSD circuit, and the RAM are connected in such a way as to allow the CPU and the OSD circuit to acquire an exclusive right to use the RAM, and (g) a bus liberation signal line over which when any one of the first and second common buses is not in use by the CPU or when neither of the first common bus and the second common bus is in use by the CPU, a message that the unused common bus or buses are made available to the OSD circuit is sent to the OSD circuit from the CPU.
Aspects of the second microcomputer architecture of the present invention are discussed. In accordance with the second microcomputer architecture of the present invention, at the same time that the CPU accesses one of the ROM and the RAM, the OSD circuit can access the other, whereby the OSD circuit can frequently access the ROM or the RAM without requesting the CPU to temporarily stop using a bus (the first or second common bus, whichever is needed by the OSD circuit). Additionally, when the OSD circuit is notified of the fact that one of the first and second common buses, that is not in use by the CPU, is available to the OSD circuit, the OSD circuit is made able to immediately start accessing the ROM or the RAM. Provision of bus switches for connecting together the first and second common buses provides conveniences when the CPU reads out data from the ROM and when the CPU reads out an instruction from the RAM.
The present invention provides a third microcomputer architecture. The third microcomputer architecture of the present invention comprises (a) a central processing unit (CPU) for instruction execution in units of n-bit widths where the number n is any integer, (b) an on-screen display (OSD) circuit for display of character information on a display screen, (c) a read only memory (ROM) for storing instructions for the CPU and character font data for the OSD circuit in storage spaces of the ROM which are used by the CPU and the OSD circuit respectively, (d) a ROM access controller for control of access to the ROM by the CPU or by the OSD circuit, (e) a data bus having a width of n bits for establishment of connection between the CPU and the ROM access controller, and (f) a ROM output data signal line having a width of 2n bits for establishment of connection between the ROM and the ROM access controller.
Aspects of the third microcomputer architecture of the present invention are discussed. In accordance with the third microcomputer architecture of the present invention, it is possible to read out ROM data of 2n bits from the ROM by an instruction of n bits from the CPU. In other words, if the ROM is accessed, via the ROM access controller, on the basis of an even address value output to the ROM from the CPU, then it is possible to read out 2n-bit ROM data, comprised of first ROM data of n bits corresponding to the even address value a
Ochi Takahiro
Tanaka Keisuke
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Tung Kee M.
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