Microcomputer using a double opcode instruction

Details Microcomputer using a double opcode instruction Microcomputer using a double opcode instruction

1979-08-31

1982-08-24

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 922

Patent

active

043464378

ABSTRACT:
A microcomputer having a 4-bit instruction register uses some double operation code (opcode) instructions thereby increasing its instruction set over the sixteen instruction limit imposed by the instruction register. During a single opcode instruction operation, a 4-bit opcode word is fetched from memory (20), is loaded into the instruction register (32), and is applied to a logic circuit (601, 603 or 621, 623). The resulting output from the logic circuit (601, 603 or 621, 623) determines the state of a latching device (610 or 630). The latching device (610 or 630) is latched into a first state in response to the output of the logic circuit, and the first opcode word stored in the instruction register controls processing of a data word to be fetched from storage. During a double opcode instruction operation, a first opcode word is fetched into the instruction register. The latching device (610 or 630) is latched into a second state in response to the output of the logic circuit. Thereafter the microcomputer fetches a second 4-bit opcode word from memory and reloads the same instruction register (32) with that second opcode word. The second state of the latching device (610 or 630) together with the second opcode word stored in the instruction register (32) subsequently control the sequence of processing a data word to be fetched from storage during execution of the double opcode instruction.

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