Microcomputer that transfers address and control to a debugging

Details Microcomputer that transfers address and control to a debugging Microcomputer that transfers address and control to a debugging

1993-01-15

1996-02-20

Swann, Tod R.

Boots, shoes, and leggings

395445, 395452, 395453, 395483, 3642384, 36424341, 3642532, 36426791, 36492692, 36496422, 36496423, 3649672, 364DIG1, 364DIG2, G06F 1200

Patent

active

054936640

ABSTRACT:
A processor according to the present invention includes a user-accessible 1 bit register for indicating, upon instruction breaking or data breaking occurring, whether any instruction or data to be debugged is existent in a cache memory or in a memory, and the 1 bit register possesses a bit issued correspondingly to a hit signal issued from the cache memory, whereby it can be known with each whether the instruction or data is existent in the cache memory or in the memory.

REFERENCES:
patent: 4675646 (1987-06-01), Lauer
patent: 5218707 (1993-06-01), Little et al.
patent: 5263153 (1993-11-01), Intrater et al.
patent: 5313608 (1994-05-01), Takai
patent: 5327567 (1994-07-01), Johnson

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