Microcomputer system including a master processor and a slave pr

Details Microcomputer system including a master processor and a slave pr Microcomputer system including a master processor and a slave pr

1988-10-21

1990-08-14

Eng, David Y.

Boots, shoes, and leggings

364230, 3642304, G06F 1516

Patent

active

049492411

ABSTRACT:
A microcomputer system includes a master processor and a coprocessor interconnected via a bus. The coprocessor supplies first, second and third signals to the master process, the first (BUSY) signal taking an active level when the coprocessor requests a wait condition of the master processor, the second (CPERR) signal taking an active level at least when the first signal is changed to the inactive level in a state of occurrence of an arithmetic exception in the coprocessor, and the third (CPEND) signal taking an active level when the coprocessor is free of execution of an instruction and of an occurrence of an arithmetic exception. When the coprocessor executes an instruction whose execution result is not required to be returned to the master processor, the master processor detects the level of the third signal and if the third signal is at the active level, the master processor starts to execute subsequent instructions irrespective of the first and second signals, in parallel with the execution of the instruction by the coprocessor.

REFERENCES:
patent: 4395758 (1983-07-01), Helenius
patent: 4509116 (1985-04-01), Lackey et al.
patent: 4547849 (1985-10-01), Louie et al.
patent: 4679166 (1987-07-01), Berger et al.
patent: 4695945 (1987-09-01), Irwin
patent: 4715013 (1987-12-01), MacGregor et al.

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