Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
2004-07-02
2009-08-18
Sough, Hyung S (Department: 2188)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C703S021000, C703S027000, C703S028000, C714S028000, C714S029000, C714S030000, C714S031000, C714S039000, C701S029000, C701S033000, C701S035000
Reexamination Certificate
active
07577560
ABSTRACT:
A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.
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Higuchi Takashi
Imada Shougo
Kanou Kouichi
Fogg & Powers LLC
Fujitsu Ten Limited
Patel Kaushikkumar
Sough Hyung S
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