Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
2005-03-29
2005-03-29
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S501000
Reexamination Certificate
active
06873332
ABSTRACT:
The microcomputer includes a CPU, a ROM, an OSD circuit, a wait signal generation circuit and a bus switch circuit. The ROM stores a program to be executed by the CPU and display data to be on-screen displayed on a display. The OSD circuit reads the display data stored in the ROM and outputs the read data to the display. The wait signal generation circuit generates a wait signal having a first level of a first time period and a second level of a second time period repeated alternately. The wait signal generation circuit determines the length of the first time period according to the amount of the display data to be read from the ROM to the OSD circuit. The bus switch circuit establishes a bus between the OSD circuit and the ROM when the wait signal is in the first level, and establishes a bus between the CPU and the ROM when the wait signal is in the second level.
REFERENCES:
patent: 5640502 (1997-06-01), Knox et al.
patent: 6219072 (2001-04-01), Tanaka et al.
patent: 6611270 (2003-08-01), Hosotani
patent: 11-102352 (1999-04-01), None
patent: 11-134291 (1999-05-01), None
Higashi Toshihiko
Matsumura Toshihiro
McDermott Will & Emery LLP
Tung Kee M.
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