Patent
1998-04-03
1999-07-27
Shah, Alpesh M.
395280, G06F 1576
Patent
active
059305231
ABSTRACT:
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
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Akao Yasushi
Hasegawa Atsushi
Hayakawa Akio
Ito Yoshitaka
Kawasaki Shumpei
Hitachi , Ltd.
Hitachi ULSI Engineering Corp.
Shah Alpesh M.
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