Microcomputer having a read protection circuit to secure the con

Details Microcomputer having a read protection circuit to secure the con Microcomputer having a read protection circuit to secure the con

1994-12-28

1997-10-21

Chan, Eddie P.

395186, G06F 1214

Patent

active

056805810

ABSTRACT:
A microcomputer has an internal program memory for storing a program and/or data, an external program memory for storing a program and/or data, a CPU for outputting a first address, for fetching an instruction stored at a location indicated by the first address from the internal program memory or the external program memory and executing the fetched instruction, and for, when the instruction instructs to read out a program or data, outputting a second address, and an internal program memory read protection circuit for receiving the first address output from the CPU and checking if the first address is present in the address space of the internal program memory, for receiving, from the CPU, the second address indicating the storage location of a program or data to be read out in accordance with the instruction and checking if the second address is present in the address space of the internal program memory. When the first address is not present in the address space of the internal program memory and the second address is present in the address space of the internal program memory, the internal program memory read protection circuit outputs a read inhibition signal to the internal program memory. The internal program memory does not execute a read access upon reception of the read inhibition signal.

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MCS-51 Family of Single Chip Microcomputers User's Manual; Intel Corporation; Jul. 1981; pp. 2-15 to 2-17, 3-1, 4-43, 4-69.

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