Microcomputer/floating point processor interface and method

Details Microcomputer/floating point processor interface and method Microcomputer/floating point processor interface and method

1999-10-01

2003-04-01

Treat, William M. (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding by plural parallel decoders

C712S214000, C712S215000, C712S219000, C712S220000, C712S222000

Reexamination Certificate

active

06542983

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microcomputers. More particularly, the present invention relates to a single chip microcomputer having a central processing execution unit and a floating point execution unit.
2. Discussion of the Related Art
System-on-chip devices (SOCs) generally microcomputers, are well-known. These devices generally include a processor (CPU), one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. One module that may be incorporated into a microcomputer is a floating point coprocessor, typically referred to as a floating point unit or FPU. A floating point unit is used to execute instructions that involve non-integer numbers. Typically, non-integer numbers are represented as a computer word divided into two parts, an exponent and a significant. Floating point units are special purpose processors designed specifically to execute arithmetic operations involving these non-integer representations of numbers.
Microcomputers with fully integrated or embedded floating point units are known. When the floating point unit is embedded in, or tightly integrated with the CPU of the microcomputer, the FPU and CPU typically share a number of operational blocks. Therefore, the interface between the FPU and CPU, both in hardware and software, is very tightly integrated. Although this level of integration typically provides high performance, such as high throughput, it can be difficult to design and build versions of the microcomputer without the FPU for sale to customers who do not want or do not require the functions of the FPU. Removing the FPU from the microcomputer can be quite difficult as a number of aspects of the microcomputer design have to be changed and in some cases removing the FPU from the microcomputer can involve a significant redesign effort.
Separate microcomputer and floating point processor systems are also known. In these systems, the microcomputer and floating point unit are typically separate integrated circuit chips and an interface is provided for the exchange of instructions and data between the CPU and the FPU. One form of interface between the CPU and the FPU uses a buffering arrangement. In these types of arrangements, the timing and synchronization requirements for execution of instructions in the CPU and FPU can be relaxed, resulting in relatively “loose” coupling between the processors. This type of system has advantages in that it is straightforward to offer the FPU as an option to the microcomputer. However, because the coupling between the CPU and FPU is loose, performance, such as throughput, may suffer because operation of the CPU and FPU is not tightly synchronized.
SUMMARY OF THE INVENTION
According to one aspect of the invention, there is provided computer system, including a single chip microcomputer including a central processing unit (CPU), a memory unit coupled to the CPU, an interface adapted to couple the CPU to a floating point instruction processing unit (FPU), an FPU present signal coupled from the interface to the CPU, floating point present signal having a first state that indicates to the CPU that an FPU is present in the single chip microcomputer and a second state that indicates to the CPU that an FPU is not present in the single chip microcomputer, where the single chip microcomputer responds to the first state of the FPU present signal to send floating point instructions across the interface to the FPU and to the second state of the signal to trap floating point instructions.
According to another aspect of the invention, the single chip microcomputer raises an exception when the FPU present signal is in the second state and a floating point instruction is trapped.
According to another aspect of the invention, the computer system, comprises a single chip microcomputer, including a central processing unit, a memory unit coupled to the CPU, an interface adapted to couple the CPU to a floating point instruction processing unit (FPU), means for indicating to the CPU that and FPU is present in the single chip microcomputer, and means, responsive to the means for indicating, for controlling the single chip microcomputer in response to the means for indicating.
According to another aspect of the invention, the computer system includes means for indicating comprises an FPU present signal having a first state that indicates that an FPU is present in the single chip microcomputer and a second state that indicates that an FPU is not present in the single chip microcomputer.
According to another aspect of the invention, the computer system includes means for controlling sends floating point instructions to the FPU when the FPU present signal is in the first state and traps floating point instructions when the FPU present signal is in the second state.
According to another aspect of the invention, the computer system comprises a single chip microcomputer including a central processing unit (CPU), a memory unit coupled to the central processing unit, an interface adapted to couple the CPU to a floating point instruction processing unit (FPU), a method of determining if an FPU is present in the computer system, the method comprises the steps of using the FPU to send an FPU present signal across the interface to the CPU where the FPU present signal has a first state indicating to the CPU that an FPU is present in the single chip microcomputer and a second state indicating to the CPU that an FPU is not present in the single chip microcomputer; and using the CPU to respond to the FPU present signal so that the single chip microcomputer sends floating point instructions across the interface to the FPU in response to the first state of the FPU present signal an traps floating point instructions in response to the second state of the FPU present signal.
According to another aspect of the invention, the computer system includes a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline including a CPU decoder pipestage and the FPU execution pipeline including an FPU decoder pipestage, the method comprises the steps of a) sending a first instruction to the CPU decoder pipestage, b) sending the first instruction to the FPU decoder pipestage, c) generating a signal indicating that the first instruction has been accepted by the CPU decoder pipestage, d) generating a signal indicating that the first instruction has been accepted by the FPU decoder pipestage, e) sending a second instruction to the CPU decoder pipestage in response to step d, and f) sending a second instruction to the FPU decoder pipestage in response to step c.
According to another aspect of the invention, the computer system further comprises the step of resending the first instruction to the CPU decoder pipestage until the signal in step d is generated.
According to another aspect of the invention, the computer further comprises the step of resending the first instruction to the FPU decoder pipestage until the signal in step c is generated
According to another aspect of the invention, the computer system includes a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline including a plurality of pipestages and the FPU pipeline including a plurality of pipestages, where each CPU pipestage in the CPU pipeline has a corresponding pipestage in the FPU pipeline, a Method of synchronizing operation of the CPU pipeline and the FPU pipeline, the method comprises the steps of, a) receiving an instruction in a first CPU pipestage, b) receiving the instruction in a corresponding first FPU pipestage, c) processing the instruction in the first CPU pipestage, d) processing the instruction in the first FPU pipestage, e) generating, by the first CPU pipestage, a first signal indicating that the instruction has been processed by first CPU pipestage and is ready to proceed to a second pipestage in the CPU pipeline, f) generating by the first FPU

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