Microcomputer equipped with DMA controller allowed to continue t

Details Microcomputer equipped with DMA controller allowed to continue t Microcomputer equipped with DMA controller allowed to continue t

1991-06-25

1997-12-09

Ellis, Richard L.

G06F 1312

Patent

active

056969899

ABSTRACT:
A microprocessor with a DMA controller for performing data transfers between a peripheral unit and a memory in response to a transfer request from the peripheral unit. The DMA controller includes a first memory block for storing information necessary to perform a current DMA data transfer and a second memory block for storing information necessary to perform the next DMA data transfer. The second DMA data transfer is initiated after completion of the first data transfer and the information stored in the second memory block is transferred to the first memory block. This process is repeated for all subsequent DMA data transfers. Each section of information stored in the first and second memory blocks includes the number of data transfers to be performed, a memory access address representing the location of the data to be transferred, and control/status information. The control/status information includes enable/disable information indicated whether another block of data is to be transferred via the DMA data transfer, thereby shortening the duration of a data transfer inhibiting state.

REFERENCES:
patent: 4475155 (1984-10-01), Oishi et al.
patent: 4847750 (1989-07-01), Daniel
patent: 5056011 (1991-10-01), Yoshitake et al.
Intel, "iAPX 86/88, 186/188 User's Manual, Hardware Reference," 1985, pp. 4-1 to 4-40.
Patent Abstracts of Japan, vol. 13, No. 253, Jun. 13, 1989 & JP-A-10 50 154, Feb. 27, 1989.
Patent Abstracts of Japan, vol. 12, No. 238, Jul. 7, 1988 & JP-A-63 029 868, Feb. 8, 1988.
Patent Abstracts of Japan, vol. 5, No. 1818, Jul. 30, 1981 & JP-A-56 060 933, May 26, 1981.

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