Microcomputer enabling high speed execution of product-sum opera

Details Microcomputer enabling high speed execution of product-sum opera Microcomputer enabling high speed execution of product-sum opera

1993-06-29

1995-10-10

Geckil, Mehmet

Boots, shoes, and leggings

3647505, 364DIG1, 364258, 3642582, G06F 752

Patent

active

054578051

ABSTRACT:
A microcomputer of the present invention includes a multiplication circuit for multiplication of a multiplier and a multiplicand data, a ripple carry adder for addition of the data and the carry from the multiplication circuit and addition of the multiplication results, a multiplication result holding register to hold the multiplication result obtained by the addition of said data and the carry from the ripple carry adder, a product-sum operation result holding register to hold the product-sum operation result obtained by addition of the multiplication results at the ripple carry adder, a selector to selectively input the data or the carry from the multiplication circuit or the multiplication result held at the multiplication result holding register to the ripple carry adder, a second selector to selectively input the data or the carry from the multiplication circuit or the product-sum operation result held at the product-sum operation result holding register to the ripple carry adder and a third selector to selectively output the multiplication result or the product-sum operation result held at the multiplication result holding register or the product-sum operation result holding register.

REFERENCES:
patent: 4958312 (1990-09-01), Ang et al.
patent: 5095456 (1992-03-01), Wong et al.
patent: 5133069 (1992-07-01), Asato et al.
patent: 5144574 (1992-09-01), Monta
patent: 5212782 (1993-05-01), Asato et al.
patent: 5218564 (1993-06-01), Covey
patent: 5231601 (1993-07-01), Stearns
patent: 5291431 (1994-03-01), Ho et al.

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