Microcomputer device having test mode substituting external RAM

Details Microcomputer device having test mode substituting external RAM Microcomputer device having test mode substituting external RAM

1986-08-25

1987-06-30

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1306

Patent

active

046775862

ABSTRACT:
A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes. Alternatively, the internal data RAM may be disabled and an external RAM used, for which a three-state or four-state instruction execution sequence is established instead of one per state to allow an operand to be transferred in on the data bus and high and low words of the accumulator transferred out; this node is very useful for checking ALU operations not otherwise accessible off-chip.

REFERENCES:
patent: 4164037 (1979-08-01), Cochran et al.
patent: 4179734 (1979-12-01), O'Leary
patent: 4298936 (1981-11-01), Shapiro
patent: 4441154 (1984-04-01), McDonough et al.
patent: 4450521 (1984-05-01), McDonough et al.
Motorola, Inc., M6805 HMOS & M146805 CMOS Family User's Manual, Prentice Hall, Englewood Cliffs, NJ, 1983, pp. 32 and 233-243.

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