Microcomputer capable of testing execution of a program with no

Details Microcomputer capable of testing execution of a program with no Microcomputer capable of testing execution of a program with no

1986-04-03

1989-09-26

Gruber, Felix D.

Boots, shoes, and leggings

3642613, 3642615, G06F 926, G06F 932

Patent

active

048705730

ABSTRACT:
A semiconductor includes a read only memory associated with an instruction decoder for decoding the instructions read out from the read only memory, and adapted to generate an address load signal when a branch instruction is read out. A program counter is provided to supply the read only memory with the address of a memory location to be read out. This program counter is adapted to be ordinarily incremented at each read-out of the read only memory and to be loaded with the branch address of the read only memory when a branch address load signal is outputted from the instruction decoder. There is also provided a circuit in response to a test mode signal for generating a branch inhibiting signal. A gate is connected to receive the branch inhibiting signal and the branch address load signal, respectively. An output of the gate is connected to an address load control input of the program counter. Thus, in the test mode, even if the branch instruction is read out, the branch instruction is blocked so that the programs in the read only memory are sequentially executed in the order of addresses without branch.

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