Microcomputer architecture utilizing an asynchronous bus between

Details Microcomputer architecture utilizing an asynchronous bus between Microcomputer architecture utilizing an asynchronous bus between

1995-05-26

1996-09-10

Lee, Thomas C.

Boots, shoes, and leggings

395285, 395308, 395500, 364DIG1, 3642286, 364231, 3642327, 364235, 3642383, 3642384, 3642385, 3642399, 364240, 3642402, 3642408, 3642409, 3642419, 3642423, 3642624, G06F 1300, G06F 1342

Patent

active

055553818

ABSTRACT:
A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and provides electrical communication to a number of peripheral devices. An asynchronous bus provides data communication between the first and second synchronous bus using handshaking signals so that the first and second clock signals operate independently of each other. The operating frequency and other parameters of the microprocessor and the first synchronous bus can be changed without requiring any changes to the second synchronous bus so that the microprocessor and the first synchronous bus can take advantage of advances in technology while allowing the second synchronous bus and the associated peripheral devices to remain compatible with previous versions of the computer system.

REFERENCES:
patent: 4205373 (1980-05-01), Shah et al.
patent: 4236203 (1980-11-01), Curley et al.
patent: 4245301 (1981-01-01), Rokutanda et al.
patent: 4263648 (1981-04-01), Stafford et al.
patent: 4287560 (1981-09-01), Forbes et al.
patent: 4293908 (1981-10-01), Bradley et al.
patent: 4315308 (1982-02-01), Jackson
patent: 4317169 (1982-02-01), Panepinto, Jr. et al.
patent: 4396995 (1983-08-01), Grau
patent: 4528626 (1985-07-01), Dean et al.
patent: 4558412 (1985-12-01), Inoshita et al.
patent: 4604683 (1986-08-01), Russ et al.
patent: 4635192 (1987-01-01), Ceccon et al.
patent: 4688166 (1987-08-01), Schneider
patent: 4695948 (1987-09-01), Blevins et al.
patent: 4703420 (1987-10-01), Irwin
patent: 4750111 (1988-06-01), Crosby, Jr. et al.
patent: 4947366 (1990-08-01), Johnson
patent: 4979097 (1990-12-01), Triolo et al.
patent: 5079696 (1992-01-01), Priem et al.
patent: 5113523 (1992-05-01), Colley et al.
patent: 5191657 (1993-03-01), Ludwig et al.
Gabel "Upgrading an old computer", PC Week, Jan. 19, 1988, v5n3 p. 517(3)--FullText copy 5 pages.
The Definicon 68020 Coprocessor, Byte, Jul. 1986, pp. 120-144.
The Conquest Turbo PC, Byte, Jul. 1986, pp. 289-291.
IBM PC Accelerators, Byte, 1986 Extra Edition.
Advance Information Sheet, IBM.RTM. PS/2.TM. Model 50/60 Compatible ChipSet.TM., Chips and Technologies, Inc., Copyright.COPYRGT., 1985, 1986, 1987.
Preliminary Specification, AT/386 CHIPSet.TM., Chips and Technologies, Inc., Copyright .COPYRGT.1985, 1986, 1987.
Product Specification, PC/AT Compatible CHIPSet.TM., Chips and Technologies, Inc., Feb., 1986.
Preliminary Specification, Advanced Memory Controller for PC/AT Compatible CHIPSet.TM., Chips and Technologies, Inc., Copyright .COPYRGT.1987.
Advance Information Sheet, IBM.RTM. PS/2.TM.Model 80 Compatible CHIPSet.TM., Chips and Technologies, Inc., Copyright .COPYRGT.1985, 1986, 1987.
Preliminary Specification, New Enhanced At (Neat.TM.) Data Book (IPC) CHIPSet.TM., Chips and Technologies, Inc., Copyright .COPYRGT.1985, 1986, 1987.
Advertisement, Personal Computer Support Group, Breakthru 286, Byte, Jan. 1987.
AST's Premium 286, Byte, Jan. 1987.
Card Converts PC to AT, Byte, Jan. 1987.
80386 Boards for PC XT and AT, Byte, Jan. 1987.
PC/AT Compatible Systems: . . . , Chips and Technologies, Inc., Sep., 1987.
Accelerator Board for 80386 Performance, Byte, Jan. 1988.
Cableless 386 Upgrade, Byte, Jan. 1988.
Ciro Cornejo, et al., "Comparing IBM's Micro Channel and Apple's NuBus," Byte, Extra Edition, 1987, pp. 83-91.

Affiliated with

Also associated with

Rating

Microcomputer architecture utilizing an asynchronous bus between does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microcomputer architecture utilizing an asynchronous bus between, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer architecture utilizing an asynchronous bus between will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1327960