Microcomputer

Details Microcomputer Microcomputer

2006-06-27

2006-06-27

Whitmore, Stacy A. (Department: 2825)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S035000, C712S041000

Reexamination Certificate

active

07069423

ABSTRACT:
A built-in memory is divided into the following two types: first memories5and7and second memories4and6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core2can simultaneously transfer two data values from the built-in memory to a DSP engine3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core2can access an external memory in parallel with the access to the second memories4and6and the first memories5and7.

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