Microcode scalable processor

Details Microcode scalable processor Microcode scalable processor

1998-07-02

2002-03-12

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C712S035000, C712S037000, C712S211000, C703S026000, C345S522000

Reexamination Certificate

active

06356995

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a processing system and more particularly to a processing system that is scalable via microcode.
BACKGROUND OF THE INVENTION
Processor architectures are utilized for a variety of functions. For example, they are utilized for media applications, for a fast fourier transfer (FFT), for a discrete cosine transform (DCT) or a finite input response (FIR) application. Conventional processor architectures are utilized to implement these functions. Each of these known architectures have problems when attempting to implement a particular function.
One conventional processor architecture comprises a digital signal processor (DSP). A DSP is typically utilized to provide a specific function such as a FFT. However, the functionality of a DSP is hardware specific, that is, the register bank associated therewith is specific to a particular application and the instructions associated therewith are specific to the function. Therefore this system is not flexible enough to accommodate various functions.
A second approach is to implement an Application Specific Signal Processor (ASSP). This ASSP has a high gate count and is not software programmable. Accordingly, the ASSP also does not provide a low cost effective solution if the processor architecture is to implement a plurality of functions.
A third approach is to provide a MMX type processor such as a Pentium processor manufactured by Intel Corporation, or a K6 processor manufactured by Advanced Micro Devices to implement a plurality of functions. However, these chips are large and complex and have high memory requirements. They typically include a large cache memory that increases the overall size of the processor. In addition there is no guarantee that the bandwidth for the MMX execution because an interrupt can occur in between the operation of the MMX instruction set.
A fourth approach is to utilize a RISC processor in conjunction with a coprocessor. However, in this approach, there are two different fetch streams and both processors fight for control of the bus. In addition, this system requires has a high memory requirement and low code density which also affects chip size.
A final approach is to utilize a general purpose media processor. However, this type of processor requires a large register file and therefore context switching is slow. In addition this approach has a large datapath, low code density and is therefore difficult to program. In addition this approach is not suitable for real time applications.
Accordingly, what is needed is a system and method that will allow a plurality of processors to provide a variety of functions while not requiring a significant amount of processing power. The system must be easy to implement utilizing existing technologies. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules and an associated pipeline if needed. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable and synthesizable. Unlike RISC or MMX type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory or dual port memory is not required while having a higher code density for a particular application.
Finally, it requires a smaller register file than a media processor, and thus context switching is faster through the general purpose processors. It does not have a big data path as a media processor. It also has higher code density and it is easier to program than a media processor application. Accordingly, a system and method in accordance with the present invention provides significant utility over existing conventional systems.


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