Microcode generation for a scalable compound instruction set mac

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364DIG1, 364DIG2, 3642318, 364230, 36493141, 3649469, 3649483, 3642624, G06F 922, G06F 938

Patent

active

053983211

ABSTRACT:
An apparatus for generating microcode in a scalable compound instruction set machine operates in response to compounding information indicating that two or more adjacent instructions are to be executed in parallel. Separate and independent microcode is held in control store for each possible instruction in a group. Microcode sequences for each instruction of a group of instructions to be executed in parallel are merged in response to the compounding information into a single microinstruction sequence.

REFERENCES:
patent: 4295193 (1981-10-01), Pomerene
patent: 4376976 (1983-03-01), Lahti et al.
patent: 4439828 (1984-03-01), Martin
patent: 4594655 (1986-06-01), Hao et al.
patent: 4825363 (1989-04-01), Baumann et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 4967343 (1990-10-01), Ngai et al.
patent: 5005118 (1991-04-01), Lenoski
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5117490 (1992-05-01), Duxbury et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5140545 (1992-08-01), Vassiliadis et al.
patent: 5155819 (1992-10-01), Watkins et al.
patent: 5163139 (1992-11-01), Haigh et al.
patent: 5229321 (1993-02-01), Iizuka
patent: 5241636 (1993-08-01), Kohn
patent: 5287467 (1994-02-01), Blaner et al.
patent: 5295249 (1994-03-01), Blaner et al.
patent: 5299319 (1994-03-01), Vassiliadis et al.
patent: 5301341 (1994-04-01), Vassiliadis et al.
patent: 5303356 (1994-04-01), Vassiliadis
Acosta, R. D., et al, "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors", IEEE Transactions on Computers, Fall, C-35 No. 9, Sep. 1986, pp. 815-828.
Anderson, V. W., et al, the IBM System/360 Model 91: "Machine Philosophy and Instruction Handling", computer structures: Principles And Examples (Siewiorek, et al, ed (McGraw-Hill, 1982, pp.276-292.
Capozzi, A. J., et al, "Non-Sequential High-Performance Processing" IBM Technical Disclosure Bulletin, vol. 27, No. 5, Oct. 1984, pp. 2842-2844.
Chan, S., et al, "Building Parallelism into the Instruction Pipeline", High Performance Systems, Dec., 1989, pp. 53-60.
Murakami, K., et al., "SIMP (Single Instruction Stream/Multiple Instruction Pipelining)": A Novel High-Speed Single Processor Architecture, Proceedings of the Sixteenth Annual Symposium On Computer Architecture, 1989, pp. 78-85.
Smith, J. E., "Dynamic Instructions Scheduling and the Astronautics ZS-1", IEEE Computer, Jul., 1989, pp. 21-35.
Smith, M. D., et al, "Limits on Multiple Instruction Issue", ASPLOS III, 1989, pp. 290-302.
Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Artihmetic Units", Computer Structures, Principles, and Examples (Siewiorek, et al ed), McGraw-Hill, 1982, pp. 293-302.
Wulf, P. S., "The WM Computer Architecture", Computer Architecture News, vol. 16, No. 1, Mar. 1988, pp. 70-84.
Jouppi, N. P., et al, "Available Instruction-Level Parallelism for Superscalar Pipelined Machines", ASPLOS III, 1989, pp. 272-282.
Jouppi, N. P., "The Non-Uniform Distribution of Instruction-Level and Machine Parallelism and its Effect on Performance", IEEE Transactions On Computers, vol. 38, No. 12, Dec., 1989, pp. 1645-1658.
Ryan, D. E., "Entails 80960: An Architecture Optimized for Embedded Control", IEEE Microcomputers, vol. 8, No. 3, Jun., 1988, pp. 63-76.
Colwell, R. P., et al, "A VLIW Architecture for a Trace Scheduling Complier", IEEE Transaction On Computers, vol. 37, No. 8, Aug., 1988, pp. 967-979.
Fisher, J. A., "The VLIW Machine: A Multi-Processor for Compiling Scientific Code", IEEE Computer, Jul., 1984, pp. 45-53.
Berenbaum, A. D., "Introduction to the CRISP Instruction Set Architecture", Proceedings Of Compcon, Spring, 1987, pp. 86-89.
Bandyopadhyay, S., et al, "Compiling for the CRISP Microprossesor", Proceedings Of Compcon, Spring, 1987, pp. 96-100.
Hennessy, J., et al, "MIPS: A VSI Processor Architecture", Proceedings Of The CMU Conference On VLSI Systems And Computations, 1981, pp. 337-346.
Patterson, E. A., "Reduced Instruction Set Computers", Communications Of The ACM, vol. 28, No. 1, Jan., 1985, pp. 8-21.
Radin, G., "The 801 Mini-Computer", IBM Journal Of Research And Development, vol. 27, No. 3, May, 1983, pp. 237-246.
Ditzel, D. R., et al, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero", Proceedings Of Compcon, Spring 1987, pp. 2-9.
Hwu, W. W., et al, "Checkpoint Repair for High-Performance Out-of-Order Execution Machines", IEEE Transactions On Computers vol. C36, No. 12, Dec., 1987, pp. 1496-1594.
Lee, J. K. F., et al, "Branch Prediction Strategies in Branch Target Buffer Design", IEEE Computer, vol. 17, No. 1. Jan. 1984, pp. 6-22.
Riseman, E. M., "The Inhibition of Potential Parallelism by Conditional Jumps", IEEE Transactions On Computers, Dec., 1972, pp. 1405-1411.
Smith, J. E., "A Study of Branch Prediction Strategies", IEEE Proceedings Of The Eight Annual Symposium On Computer Architecture, May 1981, pp. 135-148.
Archibold, James, et al, Cache Coherence Protocols: "Evaluation Using a Multiprocessor Simulation Model", ACM Transactions On Computer Systems, vol. 4, No. 4, Nov. 1986, pp. 273-398.
Baer, J. L., et al, "Multi-Level Cache Hierarchies: Organizations, Protocols, and Performance" Journal Of Parallel And Distributed Computing vol. 6, 1989, pp. 451-476.
Smith, A. J., "Cache Memorie", Computing Surveys, vol. 14, No. 3 Sep., 1982, pp. 473-530.
Smith, J. E., et al, "A Study of Instruction Cache Oraganizations and Replacement Policies", IEEE Proceedings Of The Tenth Annual International Symposium On Computer Architecture, Jun., 1983, pp. 132-137.
Vassiliadis, S., et al, "Condition Code Predictory for Fixed-Arithmetic Units", International Journal Of Electronics, vol. 66, No. 6, 1989, pp. 887-890.
Tucker, S. G., "The IBM 3090 System: An Overview", IBM Systems Journal, vol. 25, No. 1, 1986, pp. 4-19.
IBM Publication No. SA22-7200-0, Principles of Operation, IBM Enterprise Systems Architecture/370, 1988.
The Architecture Of Pipelined Computers, by Peter M. Kogge Hemisphere Publishing Corporation, 1981.
IBM Technical Disclosure Bulletin (vol. 33 No. 10A, Mar. 1991) by R. J. Eberhard.
"Self Aligning End of Instruction and Next Instruction Load", Research Disclosure, Jul. 1989, No. 303, p. 519.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Microcode generation for a scalable compound instruction set mac does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microcode generation for a scalable compound instruction set mac, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcode generation for a scalable compound instruction set mac will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-718473

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.