Microcode-controlled memory refresh apparatus for a data process

Details Microcode-controlled memory refresh apparatus for a data process Microcode-controlled memory refresh apparatus for a data process

1977-02-28

1980-08-19

Chapnick, Melvin B.

Boots, shoes, and leggings

365222, G06F 1300, G11C 700

Patent

active

042187532

ABSTRACT:
A data processing system which employs a CPU and a MOS memory, the memory requiring replenishing or refreshing periodically. The CPU includes microcode containing microinstructions, the microinstructions providing control for the CPU including control for the memory. The refreshing scheme employs apparatus for decoding of these microinstructions and for providing refreshing signals to the memory in such a manner that all non-refreshing operations of the data processing system proceed without being delayed by operation of the refreshing apparatus. The algorithm which guides the operation of the CPU includes a number of system operating modes (such as FETCH, MULTIPLY, DIVIDE, HALT, DATA CHANNEL, and others). These modes each contain an operating state designated RAC.fwdarw.MEM which indicates that a refresh signal automatically is forwarded to the MOS memory when a particular operating mode runs through its respective operating states.

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