Microcircuit fabrication and interconnection

Details Microcircuit fabrication and interconnection Microcircuit fabrication and interconnection

2008-03-25

2008-03-25

Pham, Hoai V (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S758000, C257SE23145, C257SE51040

Reexamination Certificate

active

11048231

ABSTRACT:
Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

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