Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1999-08-26
2002-06-18
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S825000, C029S829000, C029S874000
Reexamination Certificate
active
06405429
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interconnections between integrated circuits and substrates and, more particularly, to a microbeam assembly method which allows for electrical testing of an integrated circuit at speed and subsequent interconnection of the integrated circuit to a substrate.
BACKGROUND OF THE INVENTION
An essential step in the fabrication of microelectronic hardware is the step of providing electrical connections from the electronic devices to the interconnection board or substrate. As microelectronic devices such as integrated circuits become more highly integrated and more complex there is also great need for a method to fully functional test the device at speed before assembly into the circuit. Otherwise, large amounts of time are required to locate failed devices on a complex substrate containing several high lead count devices. For physically large devices the interconnection method must also be able to compensate for significant thermal expansion mismatches between the integrated circuit die and the interconnection substrate or board material. A number of unique approaches have been developed to solve some of these problems, such as TAB (tape automated bonding), beam lead bonding, and flipchip bonding.
As a point of reference, the most common approach to the interconnection of semiconductor devices involves mounting the device in a package and bonding fine wire (usually 1 mil gold or aluminum wire) from metallized pads on the device to the interior leads of the package using ultrasonic or thermocompression bonding methods. The package leads extend through the package wall and are subsequently connected to other circuitry, such as by a soldering process. In a variation on this approach, multiple copper leads (which are typically gold plated) are supplied on a polyimide tape so that the lead bonding and electrical testing processes can be highly automated. This automated lead bonding scheme is generally referred to by those skilled in the art as TAB.
FIG. 1
depicts a prior art TAB lead configuration for mounting and connecting an integrated circuit
30
to a substrate
32
using TAB leads
34
, which are typically from 1 to 1.4 mils thick and may be made from copper or other suitable conductor. A plurality of TAB leads
34
may be provided on a flexible tape for high speed automated connection to integrated circuits and full automatic (
at speed
) testing
30
. In
FIG. 1
, an integrated circuit
30
has been flipped so that integrated circuit (IC) bond pads
36
face down. The bond pads have been attached to the TAB lead
34
by thermocompression or thermosonic bonding, solder bump reflow or other bonding approaches as are know in the art. The other end of the TAB lead
34
is then attached to conductor
38
on substrate
32
, such as an MCM package, via thermocompression or thermosonic bonding, solder bump reflow or other conventional lead bonding processes. Because commercially-available TAB leads are typically fairly thick in order to be rugged enough to withstand automated TAB lead bonding processes, the prior art structure of
FIG. 1
may produce considerable stress in the projections
40
,
42
and to the connection of the projections
40
,
42
to the integrated circuit
30
or to the substrate
32
as the temperature of the structure changes. The stress is caused usually by the differential thermal expansion of the device, the substrate and/or the leads. Since the TAB lead
34
is thick and stiff, the stress is largely borne by the projections
40
,
42
and the bond to the substrate conductors
38
and the IC bond pads
36
. The bonds may fail under exposure to this repeated stress, and the reliability of the packaged integrated circuit nay thereby be degraded. Alternatively, in some applications the projection
42
is not required and the TAB lead
34
is instead bonded directly to the conductor
38
.
Several techniques have been developed for making a mechanically-sound electrical contact between the chip bond pad and an electrical lead in lead bonding applications. In one technique, the contacts are formed by wire bonding. With wire bonding, thin wires are attached via thermocompression or thermosonic bonding to a lead and a respective bond pad on the chip.
Another standard technique forms the electrical contacts through solder bumps formed on the chip bond pads. The leads are first positioned over the solder bumps on the chip. A thermode is heated to a temperature which is above the melting point of the solder and brought into contact with the leads. Sufficient force is used to insure that the leads intimately contact the solder bumps during solder reflow.
TAB and other lead bonding approaches generally produce leads that extend beyond the chip footprint (such as by 40 mils), which may be a problem in applications requiring tight spacing. In addition, the high bonding forces required to bond a copper TAB lead may damage the chip or substrate and the removal of defective TAB bonded chips from a substrate is often difficult to accomplish without damaging the substrate. Moreover, TAB leads may require stress relief to alleviate thermal expansion mismatches with the chip and substrate.
Another popular interconnect technology is the so-called “flip chip” technology first developed by IBM.
FIG. 2
depicts the flip chip approach. In flip chip, the integrated circuit
30
is flipped over so that the IC bond pads
36
face down. Connections are then made between the IC bond pads
36
and substrate conductors
38
on a substrate
32
via thermocompression or thermosonic bonding, solder reflow or other means for forming a flip chip bond between projection
44
and the substrate conductor as are known in the art. Since each integrated circuit typically includes a large number of IC bond pads
36
, and since the integrated circuit (typically formed of silicon) is made of a material having a different thermal expansion coefficient than the substrate (alumina, for example), thermal expansion differences between the integrated circuit
30
and the substrate
32
may produce mechanical stresses in the flip chip projections
44
. As the structure endures multiple thermal cycles during operation, the flip chip projections
44
may fracture or otherwise fail and integrated circuit functionality and reliability may be degraded as a result. Moreover, flip chip connections may be difficult to inspect for connection quality. In addition, flip chip solder bonding operations require solder flux, the removal of which can be difficult.
Yet another known interconnect technology is the beam lead process first developed by IBM. Beam lead technology is a semiconductor device fabrication and interconnection process whereby devices are fabricated on the semiconductor wafer with extra space (typically 8 to 12 mils) between devices. A set of interdigitated beam leads is then plated up to connect the active elements with gold conductors that can later be used to interconnect the devices to the next level circuitry. The individual devices are separated by etching the semiconductor from the back side of the wafer in the area above the plated beams so that the separated devices have individual beams extending beyond the device perimeter. The short, high conductive leads provided by the beam lead process are ideal for small high-speed diodes and transistors for microwave device applications, but the process is not useful for large lead count devices, does not permit functional testing at speed, and wastes significant wafer area to accommodate the beams.
Notwithstanding the variety of conventional lead bonding techniques available in the art, the electronics industry therefore still desires a more reliable lead bonding technology which does not require solder flux and which permits close spacing of the resulting integrated circuits. This desire for more reliable lead bonding technology seems to be becoming more important as the space available for lead bonding shrinks and as reliability requirements for resulting integrated circuits increase. Moreover, as devi
Fewer William Richard
Messner Jay Arthur
Redmond Patrick Jordan
Slemmons John Whittier
Woolston Frank John
Arbes Carl J.
Bremer Dennis C.
Honeywell Inc.
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