Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor
Reexamination Certificate
2002-01-02
2003-02-04
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
C257S678000
Reexamination Certificate
active
06515346
ABSTRACT:
RELATED FIELD OF APPLICATION
This invention relates to microchips, common inside computers and microprocessors. More specifically, to integrate electronic and photonic circuits built on the surface on semi-conducting material, such as silicon. Further more to such devices of other than flat shape, such as a rectangular thin plate. Even more specifically to cylindrical bar or pipe shape. Also to such electronic circuits having high inductance elements, such as coils and antennas. Finally, to such microchips of three-dimensional built circuits, including memory blocks, transistors, diodes, inductors, and capacitors, resonators, modulators, filters, gates, switches and lasers.
BACKGROUND OF THE INVENTION
Currently, electronic integrated circuits (IC) are built in a large array onto the surface of a large size (8″ diameter, {fraction (1/16)}″ thick) semiconductor disk, such as a silicon wafer, which is sliced from large single crystal ingot. Then said disk is cut to produce about a hundred Very Large Scale Integration (VLSI) microchips of about ½″×{fraction (
5
/
8
)}″ size dies, which are further processed by soldering electrodes (leads) and adding cover material and plastic housing (packaging) to form microchips. Said microchip work inside computers, cell-phones, sensors, controllers and microprocessors to name a few applications. Smaller size wafers and dies are also common. Currently, the largest non-experimental wafer size is 12″ diameter.
Said current embodiment—the die—perhaps small, in one dimension, relatively large in the other dimensions and require very large manufacturing facilities with clean machinery and processes in clean rooms, as well as an army of clean dressed personnel. Said process makes current microchips rather expensive (over a thousand USD per square inches). Today, the VLSI circuit density is reaching its physical limit at ever-increasing relative cost, although at slowly decreasing absolute expense. That means that said chip-making technology itself is reaching its economical limit as well. The burden of switching to 12″ wafer technology industry-wide, appears to overwhelm any individual microchip maker. One reason of reaching that technological limit is that although said IC contains several layers of intermittent or patterned metal oxide, insulator, conductor and semiconductor parts, basically, all these layers add up to a coating size, so the microchip is by all means a two dimensional object. Thus to increase the density of said IC, there are to be used ever narrower conductors and insulating gaps between. Since said IC is printed by lithography and etching. The wavelength of the exposure light—currently roentgen or “deep” ultra violet (UV)—imposes limitation on the line width. Currently, the industry is down to 12-18 nanometer line width, which is the narrowest gap between two conductors in an IC. The smallest feature size currently is 50-100 nm. The deep x-ray limits that to 25 nm. Electron tunneling limits the line width to 3-5 nm. With the current accelerated microchip technology, the industry—insisting on Moor's law—expects to reach said limits within 15-20 years. One way out is to build IC vertically on the semiconductor substrate. U.S. Pat. Nos. 4,885,615, and 5,032,896, 6,034,882 and 6,185,122 disclose such an attempt. Several of these proved to be very successful, because of advances in recent chemical-mechanical-polishing CMP and polysilicon deposition techniques, such as chemical-vapor-deposition CVD. Another new technique may contribute to 3D architecture. That is the surface monolayer initiated polymerization (SMIP), which is slow and rough today due to lack of surface tension and quick local heating and cooling capability. The microbar is just the ideal substrate for SMIP.
An objective of this invention is, not to expand said physical limit, but rather the economical one. That is to make comparable, equal or better quality microchips of about the same or achievable much smaller overall dimensions; yet marketable for only a few USD per square inches. Furthermore, to produce it in much larger (ten, hundred or thousand times larger) quantity, than it is produced today, and to produce much rapidly. That is, from crystal growth to packaging within one week, rather than half a year. Finally, to produce it without the need for any clean room operation with a single, alas large automatic tool group, holding its own microclimate. That is to produce said novel chips without direct human intervention and handling, except for tool startup, maintenance and shutdown or rebuild. Optionally, to produce continuously, without any shut down. The new manufacturing plant needs to be just a small fraction of current facility size. Such plant's environmental impact shall be marginal, shall utilize virtually all raw materials and shall consume rather small energy. The tool is to be designed and built in modules with standardized interfaces. Said modules are to be interchangeable and preferably made by different manufacturers. The emphasis of said new microchip making shifts from manpower to brainpower. That is from the daily plant operation, requiring many trained technicians to the tool and chip architecture design, requiring a few good engineers and scientists.
Another objective of this invention is to enable the integration of additional circuit elements, which require large scale coiling or closed fractal or loop antenna to add sizeable inductance or radio frequency (RF) power respectively. Du to the basic two dimensionality of current microchips, such elements are not used today. The basic bar geometry, i.e., three dimensionality of the microbar proposed here, allows the application of said elements new to Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits. Further objective is that the addition of said new elements are not to restrain the open dimensionality—at least in one (axial) direction—of the IC design to allow for size increase as integration level grows. Further more to allow for new IC design of closed loop in one (circumferential or tangential) dimension. Said closed loop IC would result in folding or turning around a flat rectangular IC to join its opposite edges, for instance wrapping it around a cylindrical surface. While left flat, such circuit closing can be achieved by wire connecting said opposite edges in the IC plain on a 2D microchip. Such flat circuit closing however consumes rather sizable chip area available for IC building and does not add inductance. One may observe that said new inductance and antenna elements could be printed on a Ball Semiconductor, manufactured by Ball Semiconductor Inc. in Texas as disclosed by U.S. Pat. No. 6,069,682 and a handful of other patents. This may be called microball, rather than a microchip. However, a microball IC designer can not increase IC size without increasing the microball diameter itself Said increase however has its natural limits. For instance, it is economical to make 1 mm diameter silicon balls by wafting but virtually impossible to make a 6 mm diameter one by other than machining, except in a space station plant, which is under no influence of gravity.
The proposed microbar has a definite advantage over a ball for being open axially. That is, a silicon bar can be processed (sized and polished) in CNC lathe and cut to different lengths to form the base material still as a single crystal for microbar manufacturing, again by special lathe processing. Further objective therefore to simplify IC manufacturing by using said lathe, for instance, using scanning laser lithography targeting the cylindrical surface of a rotating silicon round bar, rather than die image printing on a stationary substrate. Similarly all other processes common in microchip making is to be modified to lathe process. Said modifications shall represent no difficulty for the skilled in machine design and art. Said lathe shall hold its own clean microclimate, eliminating the need for clean rooms. Although said new lathe operation works on a s
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