Microarchitecture of an arithmetic unit

Details Microarchitecture of an arithmetic unit Microarchitecture of an arithmetic unit

2005-08-02

2005-08-02

Malzahn, D. H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S709000

Reexamination Certificate

active

06925480

ABSTRACT:
The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to N+1 bits. A circuit for determining the output carry value associated with the result is also provided.

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“Low Cost Overflow Generation Device for a Multiplier-Accumulator” published by IMB Technical Disclosure Bulletin, New York; vol. 28, No. 5 dated Oct. 1, 1985; pp. 1976-1977, XP000715017.
Kai-Ping Yiu; “On Sign Bit Assignment for a Vector Multiplier”; by proceedings of the IEEE, New York; vol. 64, No. 3 dated Mar. 1976; pp. 372-373; XP-002179148.
Kunitoshi Aono et al.; “Image Processor with a Reconfigurable Pipeline Architecture” proceedings of the Custom Integrated Circuits Conference, San Diego, May 15-18, 1989; New York, IEEE, US; vol. Conf. 11 dated May 15, 1989; pp. 2441-2444; XP000075588.

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