Amplifiers – With semiconductor amplifying device – Including frequency-responsive means in the signal...
Reexamination Certificate
2001-11-29
2003-09-02
Nguyen, Patricia T. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including frequency-responsive means in the signal...
C330S306000, C330S065000
Reexamination Certificate
active
06614311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a micro-wave power amplifier, and more particularly to a micro-wave power amplifier which amplifies a micro-wave signal including a plurality of carrier frequencies.
2. Description of the Related Art
As an employing device constituting a micro-wave power amplifier used in a satellite or a base station in a mobile communication system, a GaAs field effect transistor is often used.
Such a micro-wave power amplifier is required to have high power and high efficiency performances in order to accomplish reduction in size and low power consumption. In addition, a micro-wave power amplifier is further required to have a function of concurrently amplifying a plurality of signals, since data to be transmitted or received increases. To this end, a micro-wave power amplifier is required to have low mutual modulation distortion and be superior in linearity, in order to avoid exerting harmful influences on other channels.
If a micro-wave power amplifier concurrently receives a plurality of signals, the micro-wave power amplifier would have secondary distortion power at a frequency equal to a difference frequency between the received signals as well as mutual modulation distortion, due to non-linearity of the micro-wave power amplifier.
A micro-wave power amplifier is generally designed to include either a plurality of field effect transistors arranged in parallel with one another in a multi-finger pattern, or a plurality of field effect transistor chips arranged in parallel with one another, to thereby widen a gate width for accomplishing high power output.
In such a high-powered micro-wave power amplifier, if a low-frequency impedance is increased to some degrees, secondary distortion power which is generated at a frequency equal to a difference frequency between the received signals would be increased, and would be mixed with an output signal at a drain of the field effect transistor, resulting in that the mutual modulation distortion would become worse than the distortion characteristic of the micro-wave power amplifier. Consequently, the linearity of the field effect transistor could not be effectively utilized.
A field effect transistor accomplishing high power output is generally designed to be of an internal matching type transistor where a plurality of field effect transistors operating in parallel with one another are matched with one another, from the standpoint of heat radiation and general use. When such a high-powered field effect transistor receives a micro-wave signal including a plurality of carrier frequencies, secondary distortion caused by a difference frequency among carrier frequencies would deteriorate the mutual modulation distortion.
In order to solve such a problem as mentioned above, Japanese Patent No. 3060981 (Japanese Unexamined Patent Publication No. 10-233638) has suggested a micro-wave power amplifier which can prevent deterioration in distortion characteristics, even if a micro-wave signal to be amplified includes a plurality of carrier frequencies.
FIG. 1
is a circuit diagram of the micro-wave power amplifier suggested in the above-identified Publication, and
FIG. 2
is a block diagram of an example of the micro-wave power amplifier illustrated in FIG.
1
.
With reference to
FIG. 1
, the micro-wave power amplifier is comprised of a signal input terminal
77
through which a signal is input into the micro-wave power amplifier, an input signal transmission path
71
through which a signal input through the signal input terminal
77
is transmitted to a package
70
, a first capacitor
76
which is electrically connected between the signal input terminal
77
and the input signal transmission path
71
and removes dc current from the input signal, a gate bias applying terminal
75
through which a bias voltage is applied to a gate of a field effect transistor
61
arranged in the package
70
, a first quarter wavelength path
73
electrically connected to the gate bias applying terminal
75
, and transmitting a gate bias voltage applied through the gate bias applying terminal
75
, to the field effect transistor
61
, a gate protection resistor
72
electrically connected between the first quarter wavelength path
73
and the input signal transmission path
71
, a first RF terminating capacitor
74
electrically connected at one end to the first quarter wavelength path
73
and grounded (
86
) at the other end, a signal output terminal
83
through which the package
70
transmits an output signal, an output signal transmission path
78
through which the package
70
transmits an output signal to the signal output terminal
83
, a second capacitor
82
which is electrically connected between the output signal transmission path
78
and the signal output terminal
83
and removes dc current from the output signal, a drain bias applying terminal
81
through which a bias voltage is applied to a drain of the field effect transistor
61
, a second quarter wavelength path
79
electrically connected to the drain bias applying terminal
81
, and transmitting a drain bias voltage applied through the drain bias applying terminal
81
, to the field effect transistor
61
, and a second RF terminating capacitor
80
electrically connected at one end to the second quarter wavelength path
79
and grounded (
87
) at the other end.
The package
70
is comprised of the above-mentioned field effect transistor
61
having a grounded source, a gate electrode terminal
62
to which a gate of the field effect transistor
61
is electrically connected, a drain electrode terminal
63
to which a drain of the field effect transistor
61
is electrically connected, an input terminal lead
68
electrically connected between the input signal transmission path
71
and the gate electrode terminal
62
, an input mating circuit
66
electrically connected between the input terminal lead
68
and the gate electrode terminal
62
, an output terminal lead
69
electrically connected between the drain electrode terminal
63
and the output signal transmission path
78
, an output matching circuit
67
electrically connected between the drain electrode terminal
65
and the output terminal lead
69
, an difference frequency short-circuit inductor
65
electrically connected to the drain electrode terminal
63
, and a difference frequency short-circuit capacitor
64
electrically connected at one end to the difference frequency short-circuit inductor
65
, and grounded (
85
) at the other end.
The difference frequency short-circuit inductor
65
and the difference frequency short-circuit capacitor
64
define a difference frequency short-circuit circuit which is short-circuited at a difference frequency between carrier frequencies included in a micro-wave signal.
The input matching circuit
66
, the first quarter wavelength path
73
, the gate protection resistor
72
and the first RF terminating capacitor
74
define a gate bias circuit.
The output matching circuit
67
, the second quarter wavelength path
79
and the second RF terminating capacitor
80
define a drain bias circuit.
FIG. 2
illustrates an example of a micro-wave power amplifier having such a circuit structure as illustrated in FIG.
1
. The illustrated micro-wave power amplifier is of an internal matching type transistor where a plurality of field effect transistors operating in parallel with one another are matched with one another.
The micro-wave power amplifier is comprised of an input terminal
90
through which a micro-wave signal is received, a distribution circuit
91
which distributes the received micro-wave signal, matching circuit
92
ad
98
which match the received micro-wave signals with respect to an impedance by virtue of inductance and capacitance, field effect transistor chips
93
and
99
which amplify the distributed micro-wave signals, bonding patterns
97
and
101
arranged in the vicinity of drain electrodes of the field effect transistor chips
93
and
99
, respectively, difference frequency short-circuit LC circuit
Hayes & Soloway P.C.
NEC Compound Semiconductor Devices Ltd.
Nguyen Patricia T.
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