Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-01-17
2004-09-28
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
C438S018000, C438S052000, C438S083000, C438S100000, C438S101000
Reexamination Certificate
active
06797528
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication methods and systems. The present invention relates to probe assemblies of the type commonly used for testing integrated circuits (IC)
BACKGROUND OF THE INVENTION
As semiconductor integrated circuits continue to be dramatically reduced in size, the trend in electronic manufacturing has been toward increasingly smaller geometries particularly in integrated circuit technology in which a very large number of discrete circuit elements are fabricated on a single substrate or “wafer.” After fabrication, this wafer is divided into a number of rectangular-shaped chips or “dice” where each die presents a rectangular or other regular arrangement of metallized contact pads through which input/output connections are made. Although each die is eventually packaged separately, for efficiency sake, testing of the circuit formed on each die is preferably performed while the dies are still joined together on the wafer. One typical procedure is to support the wafer on a flat stage or “chuck” and to move the wafer in X, Y and Z directions relative to the head of the probing assembly so that the contacts on the probing assembly move from die to die for consecutive engagement with each die. Respective signal, power and ground lines are run to the probing assembly from the test instrumentation thus enabling each circuit to be sequentially connected to the test instrumentation.
One conventional type of probing assembly used for testing integrated circuits provides contacts that are configured as needle-like tips. These tips are mounted about a central opening formed in a probe card so as to radially converge inwardly and downwardly through the opening. When the wafer is raised beyond that point where the pads on the wafer first come into contact with these tips, the tips flex upwardly so as to skate forwardly across their respective pads thereby removing oxide buildup on the pads.
The problem with this type of probing assembly is that the needle-like tips, due to their narrow geometry, exhibit high inductance so that signal distortion is large in high frequency measurements made through these tips. Also, these tips can act in the manner of a planing tool as they wipe across their respective pads, thereby leading to excessive pad damage. This problem is magnified to the extent that the probe tips bend out of shape during use or otherwise fail to terminate in a common plane which causes the more forward ones of the tips to bear down too heavily on their respective pads.
Thus, in the course of testing semiconductor devices and circuits it becomes necessary to contact and electrically probe the devices and circuits to ascertain their function and determine failure mechanisms. To accomplish this, a finely pointed probe tip or group of finely pointed probe tips is brought into contact with the device or circuit by using pads connected to the device or circuit. As semiconductor devices become smaller and circuits denser, it becomes difficult to make electrical contact with the device with conventional probes, as the probe tips are either too large or too blunt to selectively contact only the intended device or circuit because they have a propensity to contact adjacent structures. Or, the tips are so thin as to bend when contact is attempted and slide off the probe terminal target circuit being tested. When multiple probes are required, it is often not possible to bring the correct number of probe tips close enough to each other because the size of the bodies will physically interfere with one another or will block the view of the target area being tested, thereby making alignment difficult or impossible.
As a result of these problems, pads on semiconductor devices which can number several hundred are often limited by the probe assemblies or probe rings used because of the size of the probe tips. This is especially true in the street or kerf regions between active dies on semiconductor wafers, wherein special test and process monitoring devices and circuits are often fabricated. The actual devices and monitoring structures are often very much smaller than the pads connected to them. A more compact probe assembly would allow smaller pads to be used allowing more devices in the same space or the same number of devices in a smaller space.
The present inventors thus recognize based on the foregoing, that a need exists for an acceptable micro tip that can be utilized with micro probes as semiconductor circuits continue to shrink. Users typically waste a great deal of time and effort attempting to fabricate an acceptable micro tip. To date, a reliable method for fabricating an acceptable micro tip has not been evidenced. The present inventors believe that implementing a micro tip in accordance with the invention described herein can thus solve these problems.
BRIEF SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present to provide an improved semiconductor manufacturing method and device thereof.
It is another aspect of the present invention to provide a method for forming a micro tip of a micro probe.
It is still another aspect of the present invention to provide a method for forming a micro tip of a micro probe utilizing micromachine manufacturing techniques.
It is yet another aspect of the present invention to provide a micro tip formed upon a substrate from an oxide layer configured below a conductive metal.
It is also an aspect of the present invention to provide a micro tip for a micro probe that can be efficiently mass produced and utilized with increasingly smaller sizes of integrated circuit devices.
The above and other aspects of the present invention can thus be achieved as is now described. A method and apparatus are disclosed herein for forming a micro tip for a micro probe utilized in testing semiconductor integrated circuit devices. A thick oxide layer is deposited upon a substrate initially to form the micro tip. The micro tip for the micro probe can be defined from the thick oxide layer upon the substrate through a plurality of subsequent semiconductor manufacturing operations performed upon the substrate and layers thereof. A plurality of micro tips can be mass produced and efficiently utilized in association with increasingly smaller sizes of semiconductor integrated circuit devices. The micro tip may be adapted for use with a micromachine. The micro tip may also be connected to a micro machine. The micro probe, in association with the micro tip, may comprise a micromachine. The micro tip of the micro probe may be defined utilizing a plurality of micromachine manufacturing operations.
The micro tip may be formed according to a plurality of semiconductor manufacturing operations. Thus, a first lithography operation may be performed upon the substrate and layers thereof following a deposition of the thick oxide layer upon the substrate. A first metal sputter operation may then be performed upon the substrate and layers thereof, following the first lithography operation. Thereafter, a chemical mechanical polishing (CMP) operation may be performed upon the substrate and the layers thereof. Next, a second metal sputter operation may be performed upon the substrate and layers thereof. Thereafter, a second lithographic operation can be performed upon the substrate and the layers, in order to define a shape of the micro tip. The micro tip itself may be formed between a conductive metal layer and the substrate. The conductive metal layer can comprise an aluminum layer. The substrate may comprise a silicon substrate.
REFERENCES:
patent: 6458206 (2002-10-01), Givargizov et al.
Stanley Wolf (Silicon Processing for the VLSI Era, vol. 1) (pp. 238-239, 335, and 371-373).
Lee Jeng-Han
Liu Mingo
Coleman W. David
Nguyen Khiem D
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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