Micro grid array solder interconnection structure for second lev

Details Micro grid array solder interconnection structure for second lev Micro grid array solder interconnection structure for second lev

1998-03-05

2000-05-09

Ryan, Patrick

Metal fusion bonding

Process

Plural joints

228 563, B23K 3100, B23K 3102, B23K 3514

Patent

active

060591730

ABSTRACT:
A solder interconnection between a module and printed circuit board or card is provided by a plurality of solder connections arranged in a micro grid array joining solder wettable pads on a major surface of the module to a corresponding set of solder wettable pads of the printed circuit board or card. The solder connections are column shaped with the height of each connection being at least about 1.4 times the diameter of the connection.

REFERENCES:
patent: 3871015 (1975-03-01), Lin et al.
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4604644 (1986-08-01), Beckham et al.
patent: 4605153 (1986-08-01), Van Den Brekel et al.
patent: 4967313 (1990-10-01), Berner
patent: 5216278 (1993-06-01), Lin et al.
patent: 5627406 (1997-05-01), Pace
patent: 5639696 (1997-06-01), Liang et al.
patent: 5790384 (1998-08-01), Ahmad et al.
patent: 5791911 (1998-08-01), Fasano et al.
patent: 5796590 (1998-08-01), Klein
patent: 5848702 (1998-12-01), Pakeriasamy
patent: 5861678 (1999-01-01), Schrock
patent: 5866949 (1999-02-01), Schueller
patent: 5903662 (1999-05-01), DeCarlo
patent: 5977640 (1999-05-01), Bertin et al.
Bhattacharya et al, "Repeatable, Reliable and Inexpensive Method of Flip-Flop Chip Bond", IBM Technical Disclosure Bulletin, vol. 23, No. 2, Jul. 1980, pp. 575-576.
Ecker, "Multilevel Alloy Joining System for Semiconductor Dies", IBM Technical Disclosure Bulletin, vol. 21, No. 7, Dec. 1978, pp. 2743-2746.
Coombs et al, "Chip Support Assembly", IBM Technical Disclosure Bulletin, vol. 19, No. 4, Sep. 1976, pp. 1178-1179.
Coombs, "Chip Mounting with Prestretched Joints", IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, p. 767.
Miller, "Flexible Chip Joints", IBM Technical Disclosure Bulletin, vol. 11, No. 9, Feb. 1969, p. 1173.
Miller, "Microelectronic Device Standoffs", IBM Technical Disclosure Bulletin, vol. 8, No. 3, Aug. 1965, p. 380.
Anon, "Controlled C-4 Solder Joint Elongation for Improved Thermal-Mechanical Stress Relief", IBM Technical Disclosure Bulletin, vol. 32, No. 10B, Mar. 1990, pp. 118-119.
Getten et al, "Interface Array Connector System", IBM Technical Disclosure Bulletin, vol. 17, No. 2, Jul. 1974, p. 627.
Anon, "Sandwhich Composite PCBs for Minimizing Solder Interconnection/Strain", Research Disclosure, No. 294, Oct. 1988.
In re Rose 105 USPQ 237, Mar. 22, 1955.
In re Reven 156 USPQ 679, Mar. 7, 1968.

Affiliated with

Also associated with

Rating

Micro grid array solder interconnection structure for second lev does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Micro grid array solder interconnection structure for second lev, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Micro grid array solder interconnection structure for second lev will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1056339