Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-02-26
2004-05-11
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S704000, C257S720000
Reexamination Certificate
active
06734546
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a grid array semiconductor die package having leads that extend from the bottom of the side walls, and methods for making and using the die package.
2. Discussion of the Prior Art
A semiconductor die or chip is an electrical component on which a microcircuit is built. The microcircuits can be interconnected together on the printed circuit board to form larger electrical circuits for use in radios, televisions, compact disk players, and computers, to name just a few. Because the semiconductor die is fragile, it is encased in a semiconductor die package.
The semiconductor die package includes a housing that holds the semiconductor die and conductive leads or pins that extend from the housing. The conductive leads are electrically connected to the semiconductor die within the housing. The outside ends of the leads are soldered to conductive paths on the printed circuit board. This secures the semiconductor die package to the printed circuit board and permits electrical signals to pass between the semiconductor die and other components on the printed circuit board.
As semiconductors become faster, more complex and smaller, the demand on packaging technology increases. These improvements in semiconductor performance and manufacturing drive the electrical, thermal and mechanical performance of semiconductor die packages. For example, as products with semiconductor chips become smaller and lighter, the space or area requirements of die packages have become increasingly important. In a conventional semiconductor die package having a cavity-up configuration, i.e. the active surface of the semiconductor faces away from the printed circuit board, conductive leads usually extend from one or more sides of the housing and are bent downward in an L-shape to attach to a printed circuit board (PCB) using surface-mount technology (SMT). In SMT mounting, each lead of a package is soldered onto a conductive portion of top surface of the PCB. A solder joint then maintains each lead of the die package in a fastened relationship with respect to the PCB.
In another die package configuration known as a pin grid array (PGA), the conductive leads extend from the bottom of the die package in rows and columns along the peripheral edge of the housing. PGA packages are usually utilized with a semiconductor devices requiring a large amount of conductive leads. Die packages with leads extending only from the side walls, as discussed above, usually have fewer conductive leads because of space limitations.
In a PGA, each lead is normally attached to a PCB using a mating connector or plated-through-hole (PTH) technology. A mating connector contains holes for receiving the leads of the PGA package. The PGA package is inserted into a mating connector having an array of holes that correspond to the array of conductive leads protruding from the underside of the PGA package. When using PTH technology, each lead of a package is inserted through a corresponding PTH and then soldered to form a solder joint fastening each lead in conductive contact with the PTH. In light of the additional space requirements of the conventional cavity-up semiconductor die package with leads extending from the side walls of die packages, there is a need for a cavity-up semiconductor die package having reduced size that is compatible with SMT mounting techniques. For example, BGA (Ball Grid Array) is a surface mount semiconductor package, which utilizes solder balls as its interface to the printed circuit board. The array allows for contacts to be further apart than many leaded packages.
Semiconductor die packages must also be capable of providing a stable and durable connection to the PCB. The conductive leads, which secure the die package to the PCB, must be sufficiently rigid and durable to withstand often harsh environmental conditions. Therefore, there is also a need for a high-density SMT compatible semiconductor die package with rigid, durable conductive leads that are easier and cheaper to manufacturer than conventional alternatives.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a micro grid array die package that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The present invention has been made in view of the above circumstances and has as an object to provide a cavity-up semiconductor die package manufactured with durable conductive leads that is suitable for mounting using SMT methodology.
Another object of the invention is to provide a sturdy and reliable semiconductor die package having straight leads extending from the bottom of the die package.
A further object of the invention is to provided an economical method of manufacturing a semiconductor die package having straight leads extending from the bottom of the die package.
Yet another object of the invention is to provide an economical die package with decreased design complexity and manufacturing costs.
Another object of the invention is to provide a semiconductor die package providing a stable and durable surface mount connection.
A further object of the invention is to provide methods for making semiconductor die packages having characteristics such as those discussed above.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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patent: 4839716 (1989-06-01), Butt
patent: 4839717 (1989-06-01), Phy et al.
patent: 5753857 (1998-05-01), Choi
patent: 6339191 (2002-01-01), Crane et al.
patent: 2001/0040792 (2001-11-01), Crane, Jr., et al.
patent: 0 268 181 (1998-05-01), None
patent: 2 011 727 (1979-07-01), None
Alcaria Vicente D.
Crane, Jr. Stanford W.
Jeon Myoung-Soo
Morgan & Lewis & Bockius, LLP
Pham Long
Silicon Bandwidth Inc.
Trinh (Vikki) Hoa B.
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