Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-06-28
2002-09-03
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000
Reexamination Certificate
active
06444490
ABSTRACT:
RELATED APPLICATIONS
This application is related to U.S. Ser. No. 09/105,419, now U.S. Pat. No. 5,977,640, entitled “Highly Integrated Chip-on-Chip Packaging”, by Bertin et al; and U.S. Ser. No. 09/105,477, now U.S. Pat. No. 6,225,699, entitled “Chip-on-Chip Interconnections of Varied Characteristics”, by Ference et al. The related patents are assigned to the assignee of record, were filed concurrently herewith, and are herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to packaging in semiconductor devices.
2. Background Art
In a conventional semiconductor integrated-circuit package, electrical connections to the bonding pads of a chip may be provided through a thin metal leadframe, which is typically stamped or chemically etched from strips of copper-containing materials. The leadframe includes a number of thin, closely-spaced conductive inner leads that radially extend away from the edges of the chip. The inner leads diverge away from the chip and extend through the exterior walls of the molded package where they form the external I/O leads for the package.
Some examples of conventional semiconductor integrated-circuit packages are found in the following U.S. Patents: U.S. Pat. No. 3,978,516, “Lead Frame Assembly for a Packaged Semiconductor Microcircuit” issued August 1976 to Noe; U.S. Pat. No. Re. 35,353, “Process for Manufacturing a Multi-Level Lead Frame” issued October 1996 to Tokita et al.; and U.S. Pat. No. 5,365,409, “Integrated Circuit Package Design Having an Intermediate Die-Attach Substrate Bonded to a Leadframe” issued November 1994 to Kwon et al. In the aforementioned patents, thin-film and thick-film material is used to form unique inner leads to increase speed and/or flexibility of conventional semiconductor packages.
One problem, though, with conventional semiconductor packages is that the current lead lengths are too inductive for the increased speed of operations of DRAMs. As chip sizes are reduced, the length of the lead frame segment to package edge increases, further increasing inductance. This excessive lead inductance results in degraded electrical performance of the package. Furthermore, the chip I/O pitch is limited because of the leadframe fabrication capabilities and package stresses are created when large chips are mechanically coupled to the leadframe inside a plastic encapsulated package.
SUMMARY OF THE INVENTION
It is thus an advantage of the present invention to provide thin-film connectors, such as thin-film twisted-wire pairs that eliminate the above-described and other limitations.
The advantages of the invention are realized by thin-film microflex connectors, such as thin-film microflex twisted-wire pair connectors, that electrically connect at least one chip to another level of packaging. Thus, microflex connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of a chip at increased frequencies.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
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IBM Technical Disclosure Bulletin, vol. 36, No. 12, Dec. 1993, Flex Interconnect of Multi-Chip Modules, 463-464.*
IBM Technical Disclosure Bulletin, vol. 26, No. 9, Feb. 1984, Interposer for Chip-On-Chip Module Attachment, Feinberg et al., 4590-4591.
IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mar. 1983, Chip-On-Chip Module for Assembly, Spector et al., 5315-5316.
IBM Technical Disclosure Bulletin, vol. 36 No. 12, Dec. 1993, Flex Interconnect of Multi-Chip Modules, 463-464.
IBM Technical Disclosure Bulletin, vol. 36, No. 12, Dec. 1993, Enhanced I/O Capability for Silicon on Silicon Using Solder Columns, 75-76.
IBM Technical Disclosure Bulletin, vol. 36, No. 12, Dec. 1993, Optical Flex Interconnect to Multi-Chip Modules, 669.
Novel Uses of Flexible Circuit Technology in High Performance Electronic Applications, DiStefano et al., Microelectronics International No. 39, Jan. 1996, 11-15.
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