Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
2005-07-05
2005-07-05
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
C712S230000, C712S300000, C710S068000, C707S793000, C709S249000
Reexamination Certificate
active
06915413
ABSTRACT:
A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
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patent: 6691305 (2004-02-01), Henkel et al.
MicroNews, First Quarter 1999, vol. 5, No. 1, entitled CodePack Code Compression for PowerPC Processors by Mark Game et al.
MPC565/MPC566 Reference Manual(Motorola), Oct. 15, 2000, entitled “Section 4 Burst Buffer Controller Module”.
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Fujii Dai
Hotta Takashi
Inuduka Tatsuki
Nakatsuka Yasuhiro
Shimamura Kotaro
Crowell & Moring LLP
Hitachi , Ltd.
Pan Daniel H.
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