Micro computer system

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G06F 1300, G06F 1338

Patent

active

047232056

ABSTRACT:
A microcomputer system has two central processing units, an original and one added to expand the system, each having an associated memory and being interconnected through an appropriate signal bus arrangement, however, only the first or original central processing unit employs an input/output device for inputting/outputting data; a bus controller and bus arbiter including a status signal generator are connected to the signal bus to provide addresses to permit the second or added central processing unit to be mapped onto the input/output address of the first central processing unit. The first central processing unit and its associated memory circuits and buses and the like then appear as peripherals with direct memory access from the viewpoint of the second or added central processing unit. A priority decoder is provided to insure that the first central processing unit has bus priority over the second central processing unit.

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