Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-07-09
2004-01-06
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06674297
ABSTRACT:
BACKGROUND
The present invention relates generally to interconnect devices for integrated circuits (ICs) and, more particularly, to a micro compliant interconnect apparatus for use in devices such as socket test probes.
Probe systems for both electrical testing and permanent interconnection of electronic circuits continue to grow in importance as contact densities increase. Current design trends for chips, modules and cards/boards are pushing the limits of available testing technology.
Multi-layer ceramic (MLC) substrates are well known in the art. Generally, an MLC substrate includes both ceramic layers and metal layers that are stacked to form a laminated (interdigitated) block in which the metal and ceramic layers alternate. With large and complex multi-layer ceramic substrate footprints, the interconnection integrity of the input/output (I/O) signals, and the power and ground to the source is highly dependent on the flatness of the substrate. Consequently, factors such as the substrate camber and waviness contribute to the difficulties of making a good reliable interconnection of the substrate to its source. Such factors, in turn are dependent upon the substrate design, sinter parameters, and other random factors which are nearly impossible to predict.
Accordingly, these IC devices are tested in a manner such that a reliable electrical interface must be achieved between the test probes and the IC device in order to produce reliable test results. Conventional testing devices typically utilize an array of individual conductive probes called “pogo pins”, which provide a compliant contact array to electrically interface with the I/O contacts of the IC device. Generally, the tips of the pogo pins are designed to achieve efficient electrical contact between the pogo pin tip and the tested or contacted device, and to minimize the introduction of contact resistance in the signal path. A conventional pogo pin generally includes four components: an elongated barrel, a compression spring, and a pair of probe tips extending from opposite ends of the barrel, wherein the compression spring is compressed between the inner ends of the probe tips to hold the tips in a normally extended position.
The constituent parts of a pogo pin are individually produced by machining, and are thereafter assembled into a pogo pin. As a result, the per-pin manufacturing costs are generally very high. In turn, the costs incurred by the manufacture of a socket increase in proportion to an increase in the number of external connection terminals of an IC to be tested. Furthermore, the manufacturing accuracy (i.e., variations in the position and height of a contact) has practical limitations.
In addition to the manufacturing costs thereof, the use of pogo pins can also become problematic over time. For example, one or both of the probe tips of the pogo pin may become stuck within the barrel due to a mechanical failure. As a result, physical contact is not established between the pogo pin and the external connection terminal of the IC under test. Accordingly, any defective pogo pins should be immediately replaced so that an IC is not erroneously determined to be defective. However, as suggested above, the replacement of a defective pogo pin involves a number of operations, the identification of the defective pogo pin(s), disassembly of a socket, and replacement of the defective pogo pin(s) with a non-defective one, thereby consuming manpower and time.
BRIEF SUMMARY
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a test probe interconnect apparatus for an integrated circuit device. In an exemplary embodiment, the apparatus includes an elongated housing and a probe pin extending from a first end of the housing. A biasing mechanism holds the probe pin in a normally extended position, wherein the biasing mechanism is formed from a portion of the elongated housing. In a preferred embodiment, the biasing mechanism is a flexible tab, formed from a generally rectangular section of the elongated housing and bent inwardly therein to form a cantilever.
In another embodiment, a test probe interconnect apparatus for an integrated circuit device includes an elongated housing formed from an elastic, conductive material, and a probe pin extending from a first end of the elongated housing. A biasing mechanism, formed from a portion of the elongated housing, is used for holding the probe pin in a normally extended position. The biasing mechanism further includes a first flexible tab configured into a first cantilever spring, and a second flexible tab configured into a second cantilever spring. The first and second cantilever springs are each formed from a generally rectangular section of the elongated housing, bent inwardly therein.
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Florence, Jr. Robert F.
Lopergolo Emanuele F.
Mulligan Vincent P.
Tompkins, Jr. Charles R.
Cantor & Colburn LLP
Gonzalez Floyd A.
International Business Machines - Corporation
Karlsen Ernest
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