Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-09-13
2002-10-15
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S777000, C361S774000
Reexamination Certificate
active
06465745
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit packages, and more particularly to an integrated circuit package having beam leads approaching a bonding pad from an outer periphery of the die area.
BACKGROUND ART
Semiconductor chips or wafers are used in applications including integrated circuits (ICs) or flash memory, which may be used in portable electronic devices. It is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area to minimize the size, weight, and energy consumption of devices using the semiconductor chips. ICs, whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple active and passive devices within a single chip, require suitable input/output (I/O) connections between themselves and other circuit elements or structures. These semiconductor devices are typically small and fragile and commonly carried on substrates or carrier members for support. These devices are also frequently encapsulated to protect the device from unfavorable environments, such as dust, mechanical or electrical loads, and moisture.
As the density of semiconductor chip integrated circuits increases, the density of I/O terminals, such as contacts and leads must also increase through, for example, smaller contacts and leads and/or different I/O configurations. Chip-scale packages (CSPs) offer one advantageously compact geometry, typically providing a package having an area less than approximately 1.5 times the size of the die
10
and a perimeter size roughly between 1.0 and 1.2 times the size of the die
10
. CSPs find particular applicability in portable devices such as pagers, camcorders, cell phones, cameras, personal information managers, laptop computers, and global positioning devices, where size and weight are important considerations. Of these chip-scale packages, one increasingly important high density I/O configuration is a micro-ball grid array (&mgr;BGA) package.
FIGS. 1 and 2
illustrate a chip-scale &mgr;BGA package.
FIG. 1
shows a cross-section of the &mgr;BGA package including a die
10
, an elastomer or epoxy-based thermoset adhesive
20
applied to a lower surface of die
10
, and a tape or sheet-like interposer
30
, such as an insulating organic film of polyimide. The tape
30
has an adhesive
25
formed on one side and also has metal traces or wirings
40
formed thereon or embedded therein. The metal traces
40
may be formed, for example, by depositing a thin metallic film on the tape
30
and wet-etching the metallic film. At one end, each of the metal traces
40
is attached to a respective die bonding pad
60
. The traces
40
are routed across tape
30
, as shown in
FIG. 2
, to terminate in a conductive land
45
. The lands
45
collectively form a matrix pattern and vias or holes
50
are formed in the tape
30
to overlie these lands
45
. As shown in
FIG. 1
, conductive balls
65
such as solder balls are formed in vias
50
to contact lands
45
and permit electrical connection of the I/O terminals or bonding pads
60
of the die
10
to corresponding bonding pads disposed on the surface of a printed circuit board (PCB) or other substrate. The pitch, a distance from a center line of one ball to a center line of an adjacent ball, is designated by P. An encapsulant
80
, such as an epoxy thermoset, is provided to protect the electrical connections from damage caused by unfavorable environments, such as described above.
As shown in
FIG. 2
, tape windows
70
are selectively formed at either end of die
10
in areas corresponding to the die I/O bonding pads
60
. Subsequent to connection of tape
30
to die
10
, traces
40
are connected to bonding pads
60
. One approach to connecting trace
40
and bonding pad
60
is “wire bonding”, wherein a separate wire is used to connect a bonding pad provided at an end portion of trace
40
to bonding pad
60
. The separate wire is bonded to each of the bonding pads by bonding means including ultrasonic bonding, thermal bonding, and compression bonding. Another approach to connection of traces
40
and bonding pads
60
which is better suited for the particular design constraints of &mgr;BGA and limitations of conventional manufacturing equipment is a “beam lead” connection illustrated by
FIGS. 1 and 2
. The beam lead connection is achieved by forming a portion
55
of each trace
40
to project into tape window
50
and overlie a position to be occupied by a bonding pad
60
. When a die
10
is disposed in a die receiving area of tape
30
, the bonding pads
60
are exposed within the tape window
50
and are displaced (e.g., vertically) from a projecting portion
55
of a corresponding trace
40
. The projecting portion
55
is mechanically deformed (e.g., vertically) to contact a bonding pad
60
, where it is bonded to the bonding pad
60
by conventional bonding techniques and tools, such as an ultrasonic wedge bonder or thermode, to form a beam lead connection.
However, despite its advantages, &mgr;BGA packaging is not as robust as conventional packaging and die evolution to increasingly smaller die sizes, particularly to CSPs, imposes additional constraints on design, manufacture and reliability of the die packaging. One important parameter is the bending profile of the beam lead, the exposed portion of the trace
40
extending into the tape window
70
to contact the die
10
bonding pad
60
. If the bending profile, such as the radius of curvature of the points of beam inflection, is too severe hairline cracks may develop and lead to device failure. Conventionally, to ensure that the beam lead bending profile is maintained, a predetermined tape window
70
size or width is kept constant. Another important parameter is the length of the trace
40
between the ball and the beam lead. If the trace length is too short, difficulties in formation of the short trace adversely affect the reliability of the trace, potentially leading to circuit failure. Another important parameter is ball matrix spacing or pitch. As dies
10
evolve and shrink, the available real estate for chip-scale placement of the ball matrix also shrinks, forcing a decrease in ball matrix pitches, a distance from a center line of one ball to a center line of an adjacent ball. Presently, ball matrix pitch is maintained between about 0.40 to 0.80 mm, although it is difficult to process a 0.40 to 0.50 mm pitch economically using conventional technology. If the ball matrix
itch is decreased, the available space between balls is diminished and adversely affects routing of traces between the balls, as can be understood from FIG.
2
. However, this approach advantageously preserves a desired trace length between the balls and the beam leads. Alternatively, the pitch may be maintained and the geometry or placement of the balls may instead be redistributed to utilize the available area. Disadvantageously, this alteration in the matrix geometry adversely affects tape window size and beam profile or affects the desired trace length between the balls adjacent the window and the beam leads, each potentially affecting device reliability.
SUMMARY OF INVENTION
Accordingly, a need exists in the art for an improved ball grid array package that permits improved ball matrix geometry while avoiding reliability concerns inherent in solutions affecting the aforementioned desired trace length, beam lead profile and tape window size.
This and other needs are met by the invention which provides, in one aspect, a tape automated bonding (TAB) tape carrier including an insulating tape having a die receiving section and a tape window formed in a portion of the tape die receiving section corresponding to a location of a die bonding pad. The tape carrier includes a conductive wiring pattern having a plurality of traces and a matrix of conductively filled vias electrically connecting a conductor filling the vias with predetermined traces of the conductive wiring pattern. At least one trace electrically connected to a conductively filled via dis
Fontacha Edwin R.
Valluri Viswanath
Advanced Micro Devices , Inc.
Cuneo Kamand
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